Inventor
ZOELLIN CHRISTIAN
DE44 patents
Patents
44 patentsUS9680653B1Jun 13, 2017
Cipher message with authentication instruction
IBM19 citations92
US10671532B2Jun 2, 2020
Reducing cache transfer overhead in a system
IBM7 citations84
US11586542B2Feb 21, 2023
Reducing cache transfer overhead in a system
IBM1 citations73
US11010298B2May 18, 2021
Reducing cache transfer overhead in a system
IBM2 citations73
US10831478B2Nov 10, 2020
Sort and merge instruction for a general-purpose processor
IBM3 citations73
US10824426B2Nov 3, 2020
Generating and verifying hardware instruction traces including memory data contents
IBM1 citations73
US10585800B2Mar 10, 2020
Reducing cache transfer overhead in a system
IBM3 citations73
US10579525B2Mar 3, 2020
Reducing cache transfer overhead in a system
IBM3 citations73
US10348506B2Jul 9, 2019
Determination of state of padding operation
IBM4 citations73
US10303759B2May 28, 2019
Memory preserving parse tree based compression with entropy coding
IBM2 citations73
US11797713B2Oct 24, 2023
Systems and methods for dynamic control of a secure mode of operation in a processor
IBM2 citations72
US9885748B2Feb 6, 2018
Module testing utilizing wafer probe test equipment
IBM2 citations71
US11892949B2Feb 6, 2024
Reducing cache transfer overhead in a system
IBM0 citations63
US12223098B2Feb 11, 2025
Systems and methods for dynamic control of a secure mode of operation in a processor
IBM0 citations62
US11308277B2Apr 19, 2022
Memory preserving parse tree based compression with entropy coding
IBM0 citations62
US11281469B2Mar 22, 2022
Saving and restoring machine state between multiple executions of an instruction
IBM0 citations62
US11263398B2Mar 1, 2022
Memory preserving parse tree based compression with entropy coding
IBM0 citations62
US11221850B2Jan 11, 2022
Sort and merge instruction for a general-purpose processor
IBM0 citations62
US10949212B2Mar 16, 2021
Saving and restoring machine state between multiple executions of an instruction
IBM0 citations62
US10740104B2Aug 11, 2020
Tagging target branch predictors with context with index modification and late stop fetch on tag mismatch
IBM1 citations61
US10691412B2Jun 23, 2020
Parallel sort accelerator sharing first level processor cache
IBM1 citations61
US10579332B1Mar 3, 2020
Hardware sort accelerator sharing first level processor cache
IBM1 citations61
US10936318B2Mar 2, 2021
Tagged indirect branch predictor (TIP)
IBM1 citations53
US12393399B2Aug 19, 2025
Controlling storage accesses for merge operations
IBM0 citations52
US10983797B2Apr 20, 2021
Program instruction scheduling
IBM0 citations52
US10831503B2Nov 10, 2020
Saving and restoring machine state between multiple executions of an instruction
IBM0 citations52
US10521506B2Dec 31, 2019
Memory preserving parse tree based compression with entropy coding
IBM0 citations52
US10496405B2Dec 3, 2019
Generating and verifying hardware instruction traces including memory data contents
IBM0 citations52
US10360030B2Jul 23, 2019
Efficient pointer load and format
IBM0 citations52
US10353707B2Jul 16, 2019
Efficient pointer load and format
IBM0 citations52
US10331446B2Jun 25, 2019
Generating and verifying hardware instruction traces including memory data contents
IBM0 citations52
US10169041B1Jan 1, 2019
Efficient pointer load and format
IBM0 citations52
US9716515B2Jul 25, 2017
Method for detecting end of record in variable length coded bit stream
IBM0 citations52
US10317465B2Jun 11, 2019
Integrated circuit chip and a method for testing the same
IBM0 citations51
US10006965B2Jun 26, 2018
Integrated circuit chip and a method for testing the same
IBM0 citations51
US9506986B2Nov 29, 2016
Integrated circuit chip and a method for testing the same
IBM1 citations51
US11416257B2Aug 16, 2022
Hybrid and aggregrate branch prediction system with a tagged branch orientation predictor for prediction override or pass-through
IBM0 citations50
US10956440B2Mar 23, 2021
Compressing a plurality of documents
IBM0 citations50
US10719294B2Jul 21, 2020
Hardware sort accelerator sharing first level processor cache
IBM0 citations50
US9891272B2Feb 13, 2018
Module testing utilizing wafer probe test equipment
IBM0 citations50
US10831502B2Nov 10, 2020
Migration of partially completed instructions
IBM0 citations42
US10235138B2Mar 19, 2019
Instruction to provide true random numbers
IBM0 citations42
US9679665B2Jun 13, 2017
Method for performing built-in self-tests
IBM0 citations41
US10725738B2Jul 28, 2020
Adaptive sort accelerator sharing first level processor cache
IBM0 citations40