Inventor

BADAROGLU MUSTAFA

BE38 patents

⚠️ This page may combine multiple inventors who share the name “BADAROGLU MUSTAFA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BADAROGLU MUSTAFA

QUALCOMM INC

Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor die

Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength

Semiconductor device having a gap defined therein

Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices

Contact wrap around structure

Adjacent device isolation

Self-aligned structure

Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop

Nanowire device with reduced parasitics

Standard cell circuits employing high aspect ratio voltage rails for reduced resistance

Vertically stacked nanowire field effect transistors

Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices

Minimum track standard cell circuits for reduced area

Magnetic tunnel junction (MTJ) device array

Magnetic tunnel junction (MTJ) device array

Adjacent device isolation

Folding column adder architecture for digital compute in memory

Partial sum management and reconfigurable systolic flow architectures for in-memory computation

Accumulator for digital computation-in-memory architectures

Dynamic random-access memory (DRAM) on hot compute logic for last-level-cache

Hybrid metallization interconnects for power distribution and signaling

Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methods

Digital compute in memory

Semiconductor device having a gap defined therein

Method and apparatus for source-drain junction formation in a FinFET with in-situ doping

Sub-fin device isolation

Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column

Reduced height M1 metal lines for local on-chip routing

Reduced height M1 metal lines for local on-chip routing

Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods

IMEC

Method and apparatus for minimizing the influence of a digital sub-circuit on at least partially digital circuits

Method for determining a pulse position in a signal

BADAROGLU MUSTAFA

Test circuit for testing through-silicon-vias in 3D integrated circuits

Devices comprising delay line for applying variable delay to clock signal

IMEC INTER UNI MICRO ELECTR

Method, apparatus and computer program product for determination of noise in mixed signal systems

CHARLIER OLIVIER

Method of auto calibrating a magnetic field sensor for drift and structure therefor

IMEC VZW

Method of forming gate of semiconductor device and semiconductor device having same

QUALCOMM INCORPORATED

Port landing-free low-skew signal distribution with backside metallization and buried rail