Inventor

ZHU JOHN JIANHONG

US38 patents

Patents

38 patents

US9871121B2Jan 16, 2018

Semiconductor device having a gap defined therein

QUALCOMM INC25 citations94

US9793164B2Oct 17, 2017

Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices

QUALCOMM INC23 citations94

US10354912B2Jul 16, 2019

Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)

QUALCOMM INC12 citations84

US9953979B2Apr 24, 2018

High density area efficient thin-oxide decoupling capacitor using conductive gate resistor

QUALCOMM INC8 citations83

US9379058B2Jun 28, 2016

Grounding dummy gate in scaled layout design

QUALCOMM INC13 citations83

US11404373B2Aug 2, 2022

Hybrid low resistance metal lines

QUALCOMM INC2 citations73

US10497702B2Dec 3, 2019

Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells

QUALCOMM INC3 citations73

US10483200B1Nov 19, 2019

Integrated circuits (ICs) employing additional output vertical interconnect access(es) (VIA(s)) coupled to a circuit output VIA to decrease circuit output resistance

QUALCOMM INC5 citations73

US10283526B2May 7, 2019

Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop

QUALCOMM INC5 citations73

US10163792B2Dec 25, 2018

Semiconductor device having an airgap defined at least partially by a protective structure

QUALCOMM INC3 citations73

US10043796B2Aug 7, 2018

Vertically stacked nanowire field effect transistors

QUALCOMM INC4 citations73

US9941154B2Apr 10, 2018

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

QUALCOMM INC3 citations73

US9842802B2Dec 12, 2017

Integrated circuit device featuring an antifuse and method of making same

QUALCOMM INC2 citations73

US9721891B2Aug 1, 2017

Integrated circuit devices and methods

QUALCOMM INC3 citations73

US9653399B2May 16, 2017

Middle-of-line integration methods and semiconductor devices

QUALCOMM INC3 citations73

US9620454B2Apr 11, 2017

Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods

QUALCOMM INC2 citations73

US9564361B2Feb 7, 2017

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

QUALCOMM INC2 citations73

US9502424B2Nov 22, 2016

Integrated circuit device featuring an antifuse and method of making same

QUALCOMM INC5 citations73

US9024418B2May 5, 2015

Local interconnect structures for high density

QUALCOMM INC5 citations73

US12068238B2Aug 20, 2024

Back-end-of-line (BEOL) high resistance (Hi-R) conductor layer in a metal oxide metal (MOM) capacitor

QUALCOMM INC0 citations62

US11302638B2Apr 12, 2022

Hybrid conductor integration in power rail

QUALCOMM INC0 citations62

US11239307B2Feb 1, 2022

Metal-oxide-metal capacitor from subtractive back-end-of-line scheme

QUALCOMM INC1 citations62

US12342595B2Jun 24, 2025

Transistor cell with self-aligned gate contact

QUALCOMM INC0 citations52

US11942414B2Mar 26, 2024

Integrated circuits (ICs) employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related methods

QUALCOMM INC0 citations52

US11152347B2Oct 19, 2021

Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections

QUALCOMM INC0 citations52

US11038344B2Jun 15, 2021

Shunt power rail with short line effect

QUALCOMM INC0 citations52

US10079293B2Sep 18, 2018

Semiconductor device having a gap defined therein

QUALCOMM INC1 citations52

US9196583B1Nov 24, 2015

Via material selection and processing

QUALCOMM INC0 citations52

US11973020B2Apr 30, 2024

Metal-insulator-metal capacitor with top contact

QUALCOMM INC0 citations51

US9245971B2Jan 26, 2016

Semiconductor device having high mobility channel

QUALCOMM INC0 citations49

US9478490B2Oct 25, 2016

Capacitor from second level middle-of-line layer in combination with decoupling capacitors

QUALCOMM INC0 citations42

US9472453B2Oct 18, 2016

Systems and methods of forming a reduced capacitance device

QUALCOMM INC0 citations42

US9984029B2May 29, 2018

Variable interconnect pitch for improved performance

QUALCOMM INC0 citations41

US9941156B2Apr 10, 2018

Systems and methods to reduce parasitic capacitance

QUALCOMM INC0 citations41

ZHU JOHN JIANHONG

Patents

Semiconductor device having a gap defined therein

Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices

Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)

Contact wrap around structure

Self-aligned structure

Integrated circuit devices and methods

Selective conductive barrier layer formation

High density area efficient thin-oxide decoupling capacitor using conductive gate resistor

Grounding dummy gate in scaled layout design

Hybrid low resistance metal lines

Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells

Integrated circuits (ICs) employing additional output vertical interconnect access(es) (VIA(s)) coupled to a circuit output VIA to decrease circuit output resistance

Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop

Semiconductor device having an airgap defined at least partially by a protective structure

Vertically stacked nanowire field effect transistors

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

Integrated circuit device featuring an antifuse and method of making same

Integrated circuit devices and methods

Middle-of-line integration methods and semiconductor devices

Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

Integrated circuit device featuring an antifuse and method of making same

Local interconnect structures for high density

Back-end-of-line (BEOL) high resistance (Hi-R) conductor layer in a metal oxide metal (MOM) capacitor

Hybrid conductor integration in power rail

Metal-oxide-metal capacitor from subtractive back-end-of-line scheme

Transistor cell with self-aligned gate contact

Integrated circuits (ICs) employing directly coupled metal lines between vertically-adjacent interconnect layers for reduced coupling resistance, and related methods

Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections

Shunt power rail with short line effect

Semiconductor device having a gap defined therein

Via material selection and processing

Metal-insulator-metal capacitor with top contact

Semiconductor device having high mobility channel

Capacitor from second level middle-of-line layer in combination with decoupling capacitors

Systems and methods of forming a reduced capacitance device

Variable interconnect pitch for improved performance

Systems and methods to reduce parasitic capacitance