Inventor
YANG DA
US30 patents
⚠️ This page may combine multiple inventors who share the name “YANG DA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
21 patentsUS9871121B2Jan 16, 2018
Semiconductor device having a gap defined therein
QUALCOMM INC25 citations94
US9953979B2Apr 24, 2018
Contact wrap around structure
QUALCOMM INC8 citations84
US9799560B2Oct 24, 2017
Self-aligned structure
QUALCOMM INC13 citations84
US10497702B2Dec 3, 2019
Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells
QUALCOMM INC3 citations73
US10090244B2Oct 2, 2018
Standard cell circuits employing high aspect ratio voltage rails for reduced resistance
QUALCOMM INC2 citations73
US10043796B2Aug 7, 2018
Vertically stacked nanowire field effect transistors
QUALCOMM INC4 citations73
US10032678B2Jul 24, 2018
Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices
QUALCOMM INC3 citations73
US9985014B2May 29, 2018
Minimum track standard cell circuits for reduced area
QUALCOMM INC4 citations73
US9653399B2May 16, 2017
Middle-of-line integration methods and semiconductor devices
QUALCOMM INC3 citations73
US9620454B2Apr 11, 2017
Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods
QUALCOMM INC2 citations73
US11152347B2Oct 19, 2021
Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections
QUALCOMM INC0 citations52
US10763364B1Sep 1, 2020
Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
QUALCOMM INC0 citations52
US10700204B2Jun 30, 2020
Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
QUALCOMM INC0 citations52
US10181403B2Jan 15, 2019
Layout effect mitigation in FinFET
QUALCOMM INC0 citations52
US10079293B2Sep 18, 2018
Semiconductor device having a gap defined therein
QUALCOMM INC1 citations52
US9997360B2Jun 12, 2018
Method for mitigating layout effect in FINFET
QUALCOMM INC1 citations52
US9502283B2Nov 22, 2016
Electron-beam (E-beam) based semiconductor device features
QUALCOMM INC0 citations52
US9263279B2Feb 16, 2016
Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features
QUALCOMM INC1 citations51
US9245971B2Jan 26, 2016
Semiconductor device having high mobility channel
QUALCOMM INC0 citations49
US10559501B2Feb 11, 2020
Self-aligned quadruple patterning process for Fin pitch below 20nm
QUALCOMM INC0 citations48
US9859210B2Jan 2, 2018
Integrated circuits having reduced dimensions between components
QUALCOMM INC0 citations42
CHENG JOY
3 patentsUS8114306B2Feb 14, 2012
Method of forming sub-lithographic features using directed self-assembly of polymers
CHENG JOY73 citations97
US8336003B2Dec 18, 2012
Method for designing optical lithography masks for directed self-assembly
CHENG JOY37 citations92
US8856693B2Oct 7, 2014
Method for designing optical lithography masks for directed self-assembly
CHENG JOY14 citations83