Inventor

YEAP CHOH FEI

US90 patents

⚠️ This page may combine multiple inventors who share the name “YEAP CHOH FEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YEAP CHOH FEI

QUALCOMM INC

Semiconductor device having a gap defined therein

Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices

Silicon germanium FinFET formation by Ge condensation

Integrated circuits including a FinFET and a nanostructure FET

Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)

Contact wrap around structure

Adjacent device isolation

Self-aligned structure

Memory device with adaptive voltage scaling based on error information

Merging lithography processes for gate patterning

Integrated circuit devices and methods

Three-port bit cell having increased width

Metal layers for a three-port bit cell

Selective conductive barrier layer formation

Dual write wordline memory cell

Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods

SRAM read preferred bit cell with write assist circuit

Grounding dummy gate in scaled layout design

Semiconductor device having an airgap defined at least partially by a protective structure

Nanowire device with reduced parasitics

Vertically stacked nanowire field effect transistors

Seven-transistor static random-access memory bitcell with reduced read disturbance

Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

Method and apparatus of multi threshold voltage CMOS

Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance, and related methods

Integrated circuit devices and methods

Method for asymmetrical geometrical scaling

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

Adjacent device isolation

Shared global read and write word lines

System and method of manufacturing a fin field-effect transistor having multiple fin heights

Method and apparatus of stressed FIN NMOS FinFET

Methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip

Methods for designing fin-based field effect transistors (FinFETS)

Silicon germanium read port for a static random access memory register file

Metal-insulator-metal capacitor over conductive layer

Method and apparatus of multi threshold voltage CMOS

High-K (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods

TAIWAN SEMICONDUCTOR MFG CO LTD

Method of forming backside power rails

Optimized static random access memory

Multi-gate device and related methods

Semiconductor structure and method for forming the same

Multi-gate device and related methods

Method of forming backside power rails

FREESCALE SEMICONDUCTOR INC

Semiconductor fabrication process using transistor spacers of differing widths

Isolation trench

Integrated circuit with multiple spacer insulating region widths

Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof

MOTOROLA INC

Integrated circuit structure and method therefore