Inventor

RAJAMONY RAMAKRISHNAN

US106 patents

⚠️ This page may combine multiple inventors who share the name “RAJAMONY RAMAKRISHNAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAJAMONY RAMAKRISHNAN

IBM

System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architecture

Verification of service level agreement contracts in a client server environment

Multiple disk, variable RPM data storage system for reducing power consumption

Multiple disk data storage system for reducing power consumption

Memory transaction monitoring system and user interface

Performance monitoring in a NUMA computer

System for dynamically adjusting image quality for interactive graphics applications

System and method in a collaborative data processing environment for customizing the quality of service on a per-client basis

Method and apparatus for accelerating input/output processing using cache injections

Channel ownership in a publish-subscribe system

Method and system for real time pricing of fine-grained resource purchases

Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture

Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architecture

Rule and policy promotion within a policy hierarchy

Distributed shared memory for server clusters

Application-level memory affinity control

Method for server-directed packet forwarding by a network controller based on a packet buffer threshold

System and method of managing cache hierarchies with adaptive mechanisms

Data storage on a multi-tiered disk system

Efficient identification of candidate pages and dynamic response in a NUMA computer

Interconnected processing nodes configurable as at least one non-uniform memory access (NUMA) data processing system

Scalable interruptible queue locks for shared-memory multiprocessor

Allocating a global shared memory

Reserving a global address space

Mechanism to provide reliability through packet drop detection

Mechanism to perform debugging of global shared memory (GSM) operations

Direct/indirect transmission of information using a multi-tiered full-graph interconnect architecture

System and method for handling indirect routing of information between supernodes of a multi-tiered full-graph interconnect architecture

Efficient multiple-table reference prediction mechanism

Web server architecture for improved performance

Dynamically adjusting a pre-fetch distance to enable just-in-time prefetching within a processing system

Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response

Server network controller including packet forwarding and method therefor

Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing

Distributed protocol processing in a data processing system

Conserving energy in a data processing network

Method and system for reducing cache tag bits

Issuing global shared memory operations via direct cache injection to a host fabric interface

Method and system for enhanced scheduling of memory access requests

Callee condition based communication with mobile devices

ARIMILLI LAKSHMINARAYANA B

Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture

Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks

Hardware based dynamic load balancing of message passing interface tasks

Host fabric interface (HFI) to perform global shared memory (GSM) operations

Hardware based dynamic load balancing of message passing interface tasks by modifying tasks

Method for data processing using a multi-tiered full-graph interconnect architecture

Modifying an operation of one or more processors executing message passing interface tasks

BENNER ALAN

Dual network types solution for computer interconnects

BOHRER PATRICK JOSEPH

Assist thread for injecting cache memory in a microprocessor

FREY BRADLY GEORGE

Specifying an access hint for prefetching partial cache block data in a cache hierarchy