Inventor

HUDAIT MANTU K

US45 patents

⚠️ This page may combine multiple inventors who share the name “HUDAIT MANTU K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUDAIT MANTU K

INTEL CORP

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Selective high-k dielectric film deposition for semiconductor device

Tensile strained NMOS transistor using group III-N source/drain regions

Sb-based CMOS devices

Dopant confinement in the delta doped layer using a dopant segregation barrier in quantum well structures

Dislocation-free InSb quantum well structure on Si using novel buffer architecture

Buffer layers for device isolation of devices grown on silicon

Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains

Techniques for forming contacts to quantum well transistors

Group III-V devices with multiple spacer layers

Semiconductor buffer architecture for III-V devices on silicon substrates

Methods of forming buffer layer architecture on silicon and structures formed thereby

Buffer architecture formed on a semiconductor wafer

Extreme high mobility CMOS logic

Compositionally-graded quantum-well channels for semiconductor devices

Double pass formation of a deep quantum well in enhancement mode III-V devices

Dislocation removal from a group III-V film grown on a semiconductor substrate

High hole mobility p-channel Ge transistor structure on Si substrate

Extreme high mobility CMOS logic

Techniques for forming contacts to quantum well transistors

Extreme high mobility CMOS logic

Forming arsenide-based complementary logic on a single substrate

Techniques for forming contacts to quantum well transistors

Modulation-doped multi-gate devices

Thin transition layer between a group III-V substrate and a high-k gate dielectric layer

Semiconductor buffer architecture for III-V devices on silicon substrates

Buffer layers for device isolation of devices grown on silicon

Dopant confinement in the delta doped layer using a dopant segregration barrier in quantum well structures

HUDAIT MANTU K

Stacking fault and twin blocking barrier for integrating III-V on Si

Stacking fault and twin blocking barrier for integrating III-V on Si

Forming arsenide-based complementary logic on a single substrate

High hole mobility p-channel Ge transistor structure on Si substrate

Modulation-doped multi-gate devices

High hole mobility semiconductor device

PILLARISETTY RAVI

Techniques for forming contacts to quantum well transistors

Double quantum well structures for transistors

Techniques for forming contacts to quantum well transistors

Semiconductor heterostructures to reduce short channel effects

DATTA SUMAN

Tensile strained NMOS transistor using group III-N source/drain regions

Extreme high mobility CMOS logic

Extreme high mobility CMOS logic

DATT DOT OVER A SUMAN

Extreme high mobility CMOS logic

RADOSAVLJEVIC MARKO

Self-aligned replacement metal gate process for QWFET devices

RACHMADY WILLY

Selective high-k dielectric film deposition for semiconductor device

MAJHI PRASHANT

Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains