Inventor

CRUDELE LESTER

US22 patents

⚠️ This page may combine multiple inventors who share the name “CRUDELE LESTER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CRUDELE LESTER

SPIN TRANSFER TECH INC

Perpendicular source and bit lines for an MRAM array

Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank

Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers

Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device

Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them

Smart cache design to prevent overflow for a memory device with a dynamic redundancy register

Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers

Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers

Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register

Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register

Memory array with horizontal source line and sacrificial bitline per virtual source

Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device

SPIN MEMORY INC

MRAM noise mitigation for write operations with simultaneous background operations

MRAM noise mitigation for background operations by delaying verify timing

Memory array with horizontal source line and a virtual source line

On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects

Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques

Multi-port random access memory

INTEGRATED SILICON SOLUTION CAYMAN INC

MRAM access coordination systems and methods via pipeline in parallel

MRAM access coordination systems and methods with a plurality of pipelines

Circuit engine for managing memory meta-stability

Error cache segmentation for power reduction