Inventor
MULLA DEAN
US16 patents
⚠️ This page may combine multiple inventors who share the name “MULLA DEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
12 patentsUS6948094B2Sep 20, 2005
Method of correcting a machine check error
INTEL CORP296 citations96
US6772383B1Aug 3, 2004
Combined tag and data ECC for enhanced soft error recovery from cache tag errors
INTEL CORP68 citations94
US7376877B2May 20, 2008
Combined tag and data ECC for enhanced soft error recovery from cache tag errors
INTEL CORP22 citations91
US9910470B2Mar 6, 2018
Controlling telemetry data communication in a processor
INTEL CORP10 citations84
US9710041B2Jul 18, 2017
Masking a power state of a core of a processor
INTEL CORP7 citations83
US9501129B2Nov 22, 2016
Dynamically adjusting power of non-core processor circuitry including buffer circuitry
INTEL CORP4 citations71
US12093100B2Sep 17, 2024
Hierarchical power management apparatus and method
INTEL CORP3 citations69
US9753525B2Sep 5, 2017
Systems and methods for core droop mitigation based on license state
INTEL CORP2 citations69
US10946866B2Mar 16, 2021
Core tightly coupled lockstep for high functional safety
INTEL CORP1 citations62
US11016556B2May 25, 2021
Instruction and logic for parallel multi-step power management flow
INTEL CORP0 citations60
US9720491B2Aug 1, 2017
Tracking missed periodic actions across state domains
INTEL CORP0 citations51
US10365707B2Jul 30, 2019
Instruction and logic for parallel multi-step power management flow
INTEL CORP0 citations50
INST THE DEV OF EMERGING ARCHI
2 patentsUS5664148ASep 2, 1997
Cache arrangement including coalescing buffer queue for non-cacheable data
INST THE DEV OF EMERGING ARCHI59 citations96
US5652859AJul 29, 1997
Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues
INST THE DEV OF EMERGING ARCHI84 citations96