Inventor

HIRONAKA TETSUO

JP9 patents

⚠️ This page may combine multiple inventors who share the name “HIRONAKA TETSUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SEMICONDUCTOR TECH ACAD RES CT

4 patents

US7360024B2Apr 15, 2008

Multi-port integrated cache

SEMICONDUCTOR TECH ACAD RES CT33 citations90

US7178008B2Feb 13, 2007

Register access scheduling method for multi-bank register file of a super-scalar parallel processor

SEMICONDUCTOR TECH ACAD RES CT7 citations67

US7694077B2Apr 6, 2010

Multi-port integrated cache

SEMICONDUCTOR TECH ACAD RES CT5 citations60

US7117291B2Oct 3, 2006

Memory with synchronous bank architecture

SEMICONDUCTOR TECH ACAD RES CT6 citations60

TAIYO YUDEN KK

2 patents

US9214209B2Dec 15, 2015

Semiconductor device

TAIYO YUDEN KK5 citations68

US8964460B2Feb 24, 2015

Semiconductor device having a non-volatile memory built-in

TAIYO YUDEN KK0 citations38

ISHIGURO TAKASHI

1 patent

US8952721B2Feb 10, 2015

Semiconductor device

ISHIGURO TAKASHI6 citations79

NIPPON KAYAKU KK

1 patent

US4452996AJun 5, 1984

Di(meth)acrylate esters of hydroxypivalyl hydroxypivalate ε-caprolactone condensates

NIPPON KAYAKU KK3 citations61

HIRONAKA TETSUO

1 patent

US8283945B2Oct 9, 2012

Semiconductor device

HIRONAKA TETSUO3 citations52