Inventor

CHEN TZE-CHIANG

US91 patents

⚠️ This page may combine multiple inventors who share the name “CHEN TZE-CHIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN TZE-CHIANG

IBM

Silicon-on-insulator vertical array device trench capacitor DRAM

Double SOI device with recess etch and epitaxy

Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap

Structure and method for producing low leakage isolation devices

Deep trench isolation of embedded DRAM for improved latch-up immunity

Low capacitance bipolar junction transistor and fabrication process therfor

Ambipolar synaptic devices

Method of fabricating a magnetic shift register

Method of fabricating a shiftable magnetic shift register

Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates

Method of fabricating data tracks for use in a magnetic shift register memory device

SOI transistor with polysilicon seed

Patterned strained silicon for high performance circuits

Raised base bipolar transistor structure and its method of fabrication

Process for fabricating low capacitance bipolar junction transistor

Ambipolar synaptic devices

Ambipolar synaptic devices

Hybrid junction field-effect transistor and active matrix structure

Co-integration of elemental semiconductor devices and compound semiconductor devices

Transparent conductive electrode stack containing carbon-containing material

Interdigitated back contact heterojunction photovoltaic device

Embedded junction in hetero-structured back-surface field for photovoltaic devices

Co-integration of elemental semiconductor devices and compound semiconductor devices

Transparent conductive electrode stack containing carbon-containing material

High performance CMOS circuits, and methods for fabricating same

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

Method of fabricating a magnetic shift register

Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET

Patterned SOI by formation and annihilation of buried oxide regions during processing

Use of disposable spacer to introduce gettering in SOI layer

Patterned SOI by formation and annihilation of buried oxide regions during processing

Ground-plane device with back oxide topography

Ambipolar synaptic devices

Cost-efficient high power PECVD deposition apparatus for solar cells

Hybrid junction field-effect transistor and active matrix structure

Embedded junction in hetero-structured back-surface field for photovoltaic devices

Hybrid junction field-effect transistor and active matrix structure

Hybrid heterojunction photovoltaic device

Junction field-effect quantum dot memory switch

Optical latch and synaptic switch

Quantum conductive recrystallization barrier layers

SIEMENS AG

Crack stops

Crack stops

Crack stops

Crack stops

CHEN TZE-CHIANG

Interface structure for channel mobility improvement in high-k metal gate stack

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

PCM with poly-emitter BJT access devices

INFINEON TECHNOLOGIES AG

Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof

Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof