Inventor

HUANG YU-LIEN

TW196 patents

⚠️ This page may combine multiple inventors who share the name “HUANG YU-LIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG YU-LIEN

TAIWAN SEMICONDUCTOR MFG CO LTD

Structure of S/D contact and method of making same

Vertical gate all around (VGAA) devices and methods of manufacturing the same

FinFETs with contact-all-around

Semiconductor device having a plurality of fins and method for fabricating the same

FinFETs with low source/drain contact resistance

Gate structure for semiconductor device

FinFETs with reduced parasitic capacitance and methods of forming the same

Source/drain structure and manufacturing the same

Methods for forming recesses in source/drain regions and devices formed thereof

Methods for forming recesses in source/drain regions and devices formed thereof

Asymmetric source/drain epitaxy

FinFET thermal protection methods and related structures

Method of fabricating a semiconductor device

Semiconductor device and a method for fabricating the same

Asymmetric source/drain epitaxy

Semiconductor device having a plurality of fins and method for fabricating the same

Method of forming a contact

Structure and formation method of FinFET device

Semiconductor device and method

Gate all around device structure and Fin field effect transistor (FinFET) device structure

Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure

Method of fabricating a semiconductor device

Gate structures in transistor devices and methods of forming same

Semiconductor devices

Semiconductor device and method

Self aligned contact scheme

Asymmetric source/drain epitaxy

Semiconductor device and method

TAIWAN SEMICONDUCTOR MFG

Fin-last FinFET and methods of forming same

MOS devices with strain buffer layer and methods of forming the same

FinFET structure with different fin heights and method for forming the same

FinFETs and methods for forming the same

Resolving pattern-loading issues of SiGe stressor

Source/drain structure and manufacturing the same

FETs and methods for forming the same

Semiconductor device having modified profile metal gate

Method of forming a germanium-containing FinFET

Fin-last finFET and methods of forming same

Method for fabricating a semiconductor device

Mechanisms for forming ultra shallow junction

Mechanisms for forming ultra shallow junction

HUANG YU-LIEN

Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure

High surface dopant concentration semiconductor device and method of fabricating

Doped oxide for shallow trench isolation (STI)

Replacement channels

STI structure and method of forming bottom void in same

TSAI CHUN HSIUNG

Methods for doping fin field-effect transistors

Methods of anneal after deposition of gate layers

WU CHII-MING

Mechanisms for forming ultra shallow junction

Yu de-wei

Methods of forming integrated circuits