Inventor
CHARLEBOIS STEVEN E
US5 patents
Patents
5 patentsUS7444609B2Oct 28, 2008
Method of optimizing customizable filler cells in an integrated circuit physical design process
IBM207 citations97
US7539968B2May 26, 2009
Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints
IBM11 citations82
US7194715B2Mar 20, 2007
Method and system for performing static timing analysis on digital electronic circuits
IBM14 citations82
US7886253B2Feb 8, 2011
Design structure for performing iterative synthesis of an integrated circuit design to attain power closure
IBM2 citations61
US7873923B2Jan 18, 2011
Power gating logic cones
IBM5 citations61