Inventor
GUPTA ASHWANI KUMAR
US8 patents
Patents
8 patentsUS5812839ASep 22, 1998
Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit
INTEL CORP118 citations97
US5903751AMay 11, 1999
Method and apparatus for implementing a branch target buffer in CISC processor
INTEL CORP38 citations96
US5768576AJun 16, 1998
Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor
INTEL CORP75 citations96
US5758116AMay 26, 1998
Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
INTEL CORP77 citations94
US5845100ADec 1, 1998
Dual instruction buffers with a bypass bus and rotator for a decoder of multiple instructions of variable length
INTEL CORP17 citations92
US5694589ADec 2, 1997
Instruction breakpoint detection apparatus for use in an out-of-order microprocessor
INTEL CORP37 citations92
US5944817AAug 31, 1999
Method and apparatus for implementing a set-associative branch target buffer
INTEL CORP27 citations91
US5706492AJan 6, 1998
Method and apparatus for implementing a set-associative branch target buffer
INTEL CORP22 citations91