Inventor

LIEN YU-CHUNG

US83 patents

⚠️ This page may combine multiple inventors who share the name “LIEN YU-CHUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIEN YU-CHUNG

SANDISK TECHNOLOGIES LLC

Countermeasure for reducing peak current during program operation under first read condition

Time division peak power management for non-volatile storage

Countermeasures for first read issue

Source side precharge and boosting improvement for reverse order program

Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof

Managing bit-line settling time in non-volatile memory

Power management for multi-plane read operations

Erase operation for memory device with staircase word line voltage during erase pulse

Peak and average current reduction for open block condition

State dependent VPVD voltages for more uniform threshold voltage distributions in a memory device

Lockout mode for reverse order read operation

Dynamic staggering for programming in nonvolatile memory

Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations

Charge storage memory device including ferroelectric layer between control gate electrode layers and methods of making the same

Wordline voltage overdrive methods and systems

Reduced program time for memory cells using negative bit line voltage for enhanced step up of program bias

Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption

Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof

Dynamic tier selection for program verify in nonvolatile memory

Wordline voltage overdrive methods and systems

Subgroup selection for verification

CELSRC voltage separation between SLC and XLC for SLC program average ICC reduction

MICRON TECHNOLOGY INC

Adaptive sensing time for memory operations

Memory read operation using a voltage pattern based on a read command type

Charge loss mitigation through dynamic programming sequence

Corrective read with parallel auto-read calibration in a memory sub-system

Power management for memory devices with partially good blocks

Programming delay scheme for in a memory sub-system based on memory reliability

Adaptive sensing time for memory operations

Dynamic erase operation selection using erase policy

Memory read operation using a voltage pattern based on a read command type

Memory device with fast write mode to mitigate power loss

Management of dynamic read voltage sequences in a memory subsystem

Independent sensing times

Adaptive bitline voltage for memory operations

3D NAND memory with built-in capacitor

3D NAND memory with fast corrective read

Adaptive programming delay scheme in a memory sub-system

Proximity based parity data management

Programming delay scheme for a memory sub-system based on memory reliability

Half good block handling with defective deck pre-programing in a memory sub-system

Selection of erase policy in a memory device

Dynamic read retry voltage sequences in a memory subsystem

Adaptive sensing time for memory operations

WESTERN DIGITAL TECH INC

Ramp rate control for peak and average current reduction of open blocks

Pre-charge timing control for peak current based on data latch count

Multi-stage voltage control for peak and average current reduction of open blocks

Physical defect detection in an integrated memory assembly

Dual time domain control for dynamic staggering

MICRON TECH INC

Program verify compensation in a memory device with a defective deck