Inventor

JUENGLING WERNER

US241 patents

⚠️ This page may combine multiple inventors who share the name “JUENGLING WERNER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JUENGLING WERNER

MICRON TECHNOLOGY INC

DRAM cells with vertical transistors

Methods for forming semiconductor structures

Metallization line layout

Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts

Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry

Method and apparatus for a self-aligned recessed access device (RAD) transistor gate

Method for designing photolithographic reticle layout, reticle, and photolithographic process

Method for designing photolithographic reticle layout, reticle, and photolithographic process

Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry

DRAM cells with vertical transistors

Vertical gated access transistor

Methods of forming materials over uneven surface topologies, and methods of forming insulative materials over and between conductive lines

Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry

Methods for making nearly planar dielectric films in integrated circuits

Method of forming minimally spaced word lines

Insulating materials

Method of forming materials between conductive electrical components, and insulating materials

Method of intermetal dielectric planarization by metal features layout modification

Intermetal dielectric planarization by metal features layout modification

Dual-masked isolation

Method of forming contact plugs

Dual-masked field isolation

Germanium as an antireflective coating and method of use

Process for forming both fixed and variable patterns on a single photoresist resin mask

Self-aligned isolated polysilicon plugged contacts

Systems and devices including multi-transistor cells and methods of using, making, and operating the same

Cross-hair cell wordline formation

Systems and devices including multi-gate transistors and methods of using, making, and operating the same

Data cells with drivers and methods of making and operating the same

Devices with cavity-defined gates and methods of making the same

Masking process for simultaneously patterning separate regions

Methods of providing electrical isolation in semiconductor structures

Method and algorithm for random half pitched interconnect layout with constant spacing

Systems and devices including multi-gate transistors and methods of using, making, and operating the same

DRAM cells with vertical transistors

Systems and devices including local data lines and methods of using, making, and operating the same

Vertical gated access transistor

DRAM array and electronic system

Non-planar transistor and techniques for fabricating the same

Methods of forming DRAM arrays

Semiconductor structures and memory device constructions

Methods of forming materials between conductive electrical components, and insulating materials

Bit line contacts

Method and apparatus for designing a pattern on a semiconductor surface

Minimally spaced gates and word lines

Fill pattern generation for spin-on-glass and related self-planarization deposition

Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts

Method of forming minimally spaced word lines

JUENGLING WERNER

FinFET alignment structures using a double trench flow

GLOBALFOUNDRIES INC

Fin etch and Fin replacement for FinFET integration