Inventor

FEE MICHAEL

US52 patents

⚠️ This page may combine multiple inventors who share the name “FEE MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FEE MICHAEL

IBM

Dynamic serialization of memory access in a multi-processor system

Computer system deadlock request resolution using timed pulses

Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic

Controller address contention assumption

Double data rate chaining for synchronous DDR interfaces

Quiesce handling in multithreaded environments

Maintaining order with parallel access data streams

Eliminate corrupted portions of cache during runtime

Eliminate corrupted portions of cache during runtime

Controller address contention assumption

Designated cache data backup during system operation

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

EDRAM refresh in a high performance cache architecture

Late data launch for a double data rate elastic interface

False exception for cancelled delayed requests

Dynamic data transfer control method and apparatus for shared SMP computer systems

Quiesce handling in multithreaded environments

Recovery improvement for quiesced systems

Eliminate corrupted portions of cache during runtime

Recovery improvement for quiesced systems

Bitline deletion

Multiprocessor cache buffer management

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Bypassing an encoded latch on a chip during a test-pattern scan

Bypassing an encoded latch on a chip during a test-pattern scan

Cache management using cache scope designation

Monitoring processing time in a shared pipeline

Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive

Executing an atomic primitive in a multi-core processor system

Multiprocessor cache buffer management

Computer system apparatus for stabilizing asynchronous interfaces

Early directory access of a double data rate elastic interface

AMBROLADZE EKATERINA M

On demand allocation of cache buffer slots

Dynamic pipeline cache error correction

Bitline deletion

Monitoring processing time in a shared pipeline

Method for optimizing sequential data fetches in a computer system

Error detection and recovery in a shared pipeline

BERGER DEANNA POSTLES DUNN

Dynamic trailing edge latency absorption for fetch data forwarded from a shared data/control interface

Diagnostic data collection and storage put-away station in a multiprocessor system

Multiple level linked LRU priority

Dynamically altering a pipeline controller mode based on resource availability

FEE MICHAEL

eDRAM refresh in a high performance cache architecture

Handling corrupted background data in an out of order execution environment

Memory system for error checking fetch and store data

BRONSON TIMOTHY C

Optimizing EDRAM refresh rates in a high performance cache architecture

Optimizing EDRAM refresh rates in a high performance cache architecture

DUNN BERGER DEANNA POSTLES

Preemptive in-pipeline store compare resolution

Preemptive in-pipeline store compare resolution

COLLURA ADAM B

Clock-based debugging for embedded dynamic random access memory element in a processor core