Inventor

WU SHENG-YU

TW55 patents

⚠️ This page may combine multiple inventors who share the name “WU SHENG-YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU SHENG-YU

TAIWAN SEMICONDUCTOR MFG CO LTD

Dummy flip chip bumps for reducing stress

Contact area design for solder bonding

Conical-shaped or tier-shaped pillar connections

Contact area design for solder bonding

Interconnection structure and method of forming same

Display device and manufacturing method thereof

Scheme for connector site spacing and resulting structures

Semiconductor device having conductive bumps of varying heights

Dummy flip chip bumps for reducing stress

Semiconductor device having conductive bumps of varying heights

Connector structure and method of forming same

Methods and apparatus for bump-on-trace chip packaging

Semiconductor device, integrated circuit structure using the same, and manufacturing method thereof

Semiconductor device and bump formation process

Connector structure and method of forming same

Bump-on-trace design for enlarge bump-to-trace distance

Conical-shaped or tier-shaped pillar connections

Scheme for connector site spacing and resulting structures

Scheme for connector site spacing and resulting structures

Solderless interconnection structure and method of forming same

Display device and manufacturing method thereof

Conductive structures and redistribution circuit structures

Solderless interconnection structure and method of forming same

Semiconductor device

Connector structure and method of forming same

Dummy flip chip bumps for reducing stress

Redistribution circuit structures and methods of forming the same

Bump-on-trace design for enlarge bump-to-trace distance

Connector structure and method of forming same

Solderless interconnection structure and method of forming same

Package on-package process for applying molding compound

Semiconductor structure and manufacturing method of the same

Semiconductor structure and manufacturing method of the same

TAIWAN SEMICONDUCTOR MFG

Dummy flip chip bumps for reducing stress

Scheme for connector site spacing and resulting structures

Bump-on-trace design for enlarge bump-to-trace distance

Methods and apparatus for bump-on-trace chip packaging

Apparatus and method for three dimensional integrated circuits

Solder mask shape for BOT laminate packages

Structure and method for bump to landing trace ratio

KUO TIN-HAO

Conical-shaped or tier-shaped pillar connections

Elongated bump structure for semiconductor devices

WU SHENG-YU

Dummy flip chip bumps for reducing stress

Semiconductor devices and methods of manufacturing and packaging thereof

ADVANCED SEMICONDUCTOR ENG

Flip chip packaging process

TSAI PEI-CHUN

Connecting function chips to a package to form package-on-package

HON HAI PREC IND CO LTD

Eject mechanism

LIN YEN-LIANG

Elongated bumps in integrated circuit devices

YU CHEN-HUA

Structure and method for bump to landing trace ratio

CHEN MENG-TSE

Package-on-package process for applying molding compound