Inventor

CHEN SHIH-CHENG

TW90 patents

⚠️ This page may combine multiple inventors who share the name “CHEN SHIH-CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN SHIH-CHENG

TAIWAN SEMICONDUCTOR MFG CO LTD

Gate isolation for multigate device

Uniform gate width for nanostructure devices

Methods of fabricating a FinFET device with wrap-around silicide source/drain structure

Semiconductor device structure and methods of forming the same

Gate isolation for multigate device

Uniform gate width for nanostructure devices

Semiconductor structure and method for forming the same

FET with wrap-around silicide and fabrication methods thereof

Semiconductor device structure and methods of forming the same

Gate all around transistor with dual inner spacers

Multi-gate device and related methods

FET with wrap-around silicide and fabrication methods thereof

Semiconductor device structure and methods of forming the same

Semiconductor devices and methods of manufacture

Semiconductor device with facet S/D feature and methods of forming the same

Semiconductor device and manufacturing method thereof

Semiconductor device and method

Latch-up prevention

Methods of forming silicide contact in field-effect transistors

Integrated circuit with bottom dielectric insulators and fin sidewall spacers for reducing source/drain leakage currents

Integrated circuit with nanostructure transistors and bottom dielectric insulators

Reduction of gate-drain capacitance

Multi-gate device and related methods

Semiconductor device and method

Semiconductor device structure and methods of forming the same

Uniform gate width for nanostructure devices

Semiconductor devices with backside power rail and methods of fabrication thereof

Semiconductor devices and methods of manufacture

Method for manufacturing semiconductor structure with isolation feature

Method for forming epitaxial source/drain features and semiconductor devices fabricated thereof

Semiconductor device

Hybrid source drain regions formed based on same fin and methods forming same

Contact structure for stacked multi-gate device

Latch-up prevention

Methods of forming silicide contact in field-effect transistors

Semiconductor device structure with silicide layer

Semiconductor device structure and methods of forming the same

Semiconductor device

Methods of forming silicide contact in field-effect transistors

Method for forming epitaxial source/drain features and semiconductor devices fabricated thereof

Contact structure for stacked multi-gate device

Semiconductor device structure with silicide

Reduction of gate-drain capacitance

UNITED MICROELECTRONICS CORP

Method of forming high dielectric constant dielectric layer by atomic layer deposition

Semiconductor device having contact plug connected to gate structure on PMOS region

Semiconductor device

Semiconductor device having contact plug connected to gate structure on PMOS region

Semiconductor device having contact plug connected to gate structure on PMOS region

NOVATEK MICROELECTRONICS CORP

Electronic device and fingerprint sensing control method thereof

Electronic device, fingerprint sensing control method and fingerprint scanning control method