Inventor
CHEN JIASHENG
TW30 patents
⚠️ This page may combine multiple inventors who share the name “CHEN JIASHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ADVANCED MICRO DEVICES INC
17 patentsUS10509596B2Dec 17, 2019
Extreme-bandwidth scalable performance-per-watt GPU architecture
ADVANCED MICRO DEVICES INC4 citations73
US10817302B2Oct 27, 2020
Processor support for bypassing vector source operands
ADVANCED MICRO DEVICES INC2 citations72
US11789732B2Oct 17, 2023
Arithmetic logic unit register sequencing
ADVANCED MICRO DEVICES INC0 citations62
US11768664B2Sep 26, 2023
Processing unit with mixed precision operations
ADVANCED MICRO DEVICES INC1 citations62
US11237827B2Feb 1, 2022
Arithemetic logic unit register sequencing
ADVANCED MICRO DEVICES INC0 citations62
US11494192B2Nov 8, 2022
Pipeline including separate hardware data paths for different instruction types
ADVANCED MICRO DEVICES INC0 citations61
US10656951B2May 19, 2020
Pipeline including separate hardware data paths for different instruction types
ADVANCED MICRO DEVICES INC1 citations61
US11625807B2Apr 11, 2023
Low power and low latency GPU coprocessor for persistent computing
ADVANCED MICRO DEVICES INC0 citations60
US10929944B2Feb 23, 2021
Low power and low latency GPU coprocessor for persistent computing
ADVANCED MICRO DEVICES INC1 citations60
US11762658B2Sep 19, 2023
Matrix multiplication unit with flexible precision operations
ADVANCED MICRO DEVICES INC0 citations52
US11630667B2Apr 18, 2023
Dedicated vector sub-processor system
ADVANCED MICRO DEVICES INC0 citations52
US11409536B2Aug 9, 2022
Pairing SIMD lanes to perform double precision operations
ADVANCED MICRO DEVICES INC0 citations51
US12067401B2Aug 20, 2024
Stream processor with low power parallel matrix multiply pipeline
ADVANCED MICRO DEVICES INC0 citations49
US11880683B2Jan 23, 2024
Packed 16 bits instruction pipeline
ADVANCED MICRO DEVICES INC0 citations49
US11347827B2May 31, 2022
Hybrid matrix multiplication pipeline
ADVANCED MICRO DEVICES INC0 citations48
US10360177B2Jul 23, 2019
Method and processing apparatus for gating redundant threads
ADVANCED MICRO DEVICES INC0 citations48
US10970081B2Apr 6, 2021
Stream processor with decoupled crossbar for cross lane operations
ADVANCED MICRO DEVICES INC0 citations44
INTEL CORP
7 patentsUS11842423B2Dec 12, 2023
Dot product operations on sparse matrix elements
INTEL CORP4 citations86
US12189571B2Jan 7, 2025
Dual pipeline parallel systolic array
INTEL CORP1 citations63
US12198222B2Jan 14, 2025
Architecture for block sparse operations on a systolic array
INTEL CORP0 citations62
US12236238B2Feb 25, 2025
Large integer multiplication enhancements for graphics environment
INTEL CORP0 citations59
US12487824B2Dec 2, 2025
Immediate offset of load store and atomic instructions
INTEL CORP0 citations52
US12086205B2Sep 10, 2024
Random sparsity handling in a systolic array
INTEL CORP0 citations52
US12190158B2Jan 7, 2025
Using sparsity metadata to reduce systolic array power consumption
INTEL CORP0 citations51