Inventor

LUE HANG-TING

TW255 patents

⚠️ This page may combine multiple inventors who share the name “LUE HANG-TING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUE HANG-TING

MACRONIX INT CO LTD

Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays

Plane decoding method and device for three dimensional memories

Vertical thin-channel memory

U-shaped vertical thin-channel memory

3D independent double gate flash memory

Multiple-bit-per-cell, independent double gate, vertical channel memory

Method for making multilayer connection structure

Memory device, manufacturing method and operating method of the same

Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same

Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer

Operation scheme for spectrum shift in charge trapping non-volatile memory

High-κ capped blocking dielectric bandgap engineered SONOS and MONOS

Depletion mode bandgap engineered memory

Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same

3D array arranged for memory and in-memory sum-of-products operations

Blocking dielectric engineered charge trapping memory cell with high speed erase

3D memory array device and method for multiply-accumulate

U-shaped vertical thin-channel memory

Sub-block erase

3D independent double gate flash memory on bounded conductor layer

Bandgap-engineered memory with multiple charge trapping layers storing charge

Assist gate structures for three-dimensional (3D) vertical gate array memory structure

P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals

Integrated circuit self aligned 3D memory array and manufacturing method

Stacked non-volatile memory device and methods for fabricating the same

Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays

Methods of operating p-channel non-volatile memory devices

Operating method of non-volatile memory device

Bandgap engineered split gate memory

Program/erase method for P-channel charge trapping memory device

LUE HANG-TING

Three-dimensional stacked and-type flash memory structure and methods of manufacturing and operating the same hydride

Integrated circuit self aligned 3D memory array and manufacturing method

Integration of 3D stacked IC device with peripheral circuits

Memory architecture of 3D NOR array

Silicon on insulator and thin film transistor bandgap engineered split gate memory

Integrated circuit self aligned 3D memory array and manufacturing method

Multi-gate bandgap engineered memory

3D NAND flash memory

Floating gate memory device with interpoly charge trapping structure

Depletion-mode charge-trapping flash device

LUNG HSIANG-LAN

3D memory array arranged for FN tunneling program and erase

3D memory array arranged for FN tunneling program and erase

3D two bit-per-cell NAND flash memory

Integrated circuit 3D memory array and manufacturing method

CHEN SHIH-HUNG

Memory architecture of 3D array with alternating memory string orientation and string select structures

Reduced number of masks for IC device with stacked contact levels

HUNG CHUN-HSIUNG

Memory architecture of 3D array with diode in memory string

3D memory array with improved SSL and BL contact layout

SHIH YEN-HAO

Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory

MACRONIX INTERNAT CO INTL

Operation scheme with charge balancing erase for charge trapping non-volatile memory