Inventor
BHAVNAGARWALA AZEEZ J
US10 patents
⚠️ This page may combine multiple inventors who share the name “BHAVNAGARWALA AZEEZ J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
7 patentsUS6977519B2Dec 20, 2005
Digital logic with reduced leakage
IBM78 citations97
US6839299B1Jan 4, 2005
Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells
IBM21 citations92
US6788566B1Sep 7, 2004
Self-timed read and write assist and restore circuit
IBM35 citations92
US6683805B2Jan 27, 2004
Suppression of leakage currents in VLSI logic and memory circuits
IBM41 citations92
US7259986B2Aug 21, 2007
Circuits and methods for providing low voltage, high performance register files
IBM12 citations83
US7968450B2Jun 28, 2011
Methods for incorporating high dielectric materials for enhanced SRAM operation and structures produced thereby
IBM4 citations63
US6791886B1Sep 14, 2004
SRAM cell with bootstrapped power line
IBM4 citations62
LSI LOGIC CORP
3 patentsUS6861739B1Mar 1, 2005
Minimum metal consumption power distribution network on a bonded die
LSI LOGIC CORP30 citations92
US6529400B1Mar 4, 2003
Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cells
LSI LOGIC CORP35 citations92
US6515893B1Feb 4, 2003
Source pulsed, low voltage CMOS SRAM cell for fast, stable operation
LSI LOGIC CORP30 citations91