Inventor
AIYANDRA RAJESH SUBRAYA
DE8 patents
Patents
8 patentsUS10797012B2Oct 6, 2020
Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
DIALOG SEMICONDUCTOR UK LTD5 citations80
US10083926B1Sep 25, 2018
Stress relief solutions on WLCSP large/bulk copper plane design
DIALOG SEMICONDUCTOR UK LTD11 citations78
US10636742B2Apr 28, 2020
Very thin embedded trace substrate-system in package (SIP)
DIALOG SEMICONDUCTOR UK LTD4 citations70
US12100679B2Sep 24, 2024
Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
DIALOG SEMICONDUCTOR UK LTD0 citations59
US11495567B2Nov 8, 2022
Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
DIALOG SEMICONDUCTOR UK LTD1 citations59
US11309255B2Apr 19, 2022
Very thin embedded trace substrate-system in package (SIP)
DIALOG SEMICONDUCTOR UK LTD0 citations59
US10396004B2Aug 27, 2019
Reduction of cross talk in WLCSP's through laser drilled technique
DIALOG SEMICONDUCTOR UK LTD1 citations59
US10607912B2Mar 31, 2020
Reduction of cross talk in WLCSP's through laser drilled technique
DIALOG SEMICONDUCTOR UK LTD0 citations48