Inventor
MCKENNA JONATHAN M
US5 patents
Patents
5 patentsUS6731179B2May 4, 2004
System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI)
IBM96 citations96
US6624031B2Sep 23, 2003
Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
IBM62 citations96
US6188234B1Feb 13, 2001
Method of determining dielectric time-to-breakdown
IBM22 citations91
US7132325B2Nov 7, 2006
Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
IBM10 citations73
US6770907B2Aug 3, 2004
Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure
IBM5 citations73