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Inventor
SATOH SHIGENOBU
JP
2 patents
Patents
2 patents
US7146592B2
Dec 5, 2006
Integrated logic circuit and hierarchical design method thereof
FUJITSU LTD
0 citations
46
US6924666B2
Aug 2, 2005
Integrated logic circuit and hierarchical design method thereof
FUJITSU LTD
0 citations
46