Inventor

NAKATSUKA YASUHIRO

US55 patents

⚠️ This page may combine multiple inventors who share the name “NAKATSUKA YASUHIRO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAKATSUKA YASUHIRO

HITACHI LTD

Vehicle control system

Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Image data processor for processing pixel data in block buffer

Graphic processor and data processing system

Data processor having unified memory architecture providing priority memory access

Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory

Parallel processing apparatus and method capable of processing plural instructions in parallel or successively

Information processor and information processing system utilizing clock signal

Parallel processing apparatus and method capable of switching parallel and successive processing modes

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Parallel processing apparatus and method capable of switching parallel and successive processing modes

Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation

Data processing apparatus and register address translation method thereof

Computer having a parallel operating capability

Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation

Data processor having unified memory architecture providing priority memory access

Picture processing apparatus and picture processing method

Graphics drawing device with hidden surface processing

Information processor and information processing system utilizing clock signal

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Vehicle control system

Three-dimensional graphic display device

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Data processor apparatus and shading apparatus

Image processing device and system using the same

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

Method and apparatus for controlling one or more hierarchical memories using a virtual storage scheme and physical to virtual address translation

Information processing apparatus having micro instructions stored both in on-chip ROM and off-chip memory

Instruction decode method and arrangement suitable for a decoder of microprocessors

Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein

Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein

Semiconductor memory having an arithmetic function and a terminal arrangement for coordinating operation with a higher processor

Perspective projection calculation devices and methods

Perspective projection calculation devices and methods

Information processor and information processing system utilizing interface for synchronizing clock signal

Data processor having unified memory architecture using register to optimize memory access

Graphic processor and data processing system

Image processing device and system using the same

RENESAS TECH CORP

Data processing apparatus and shading apparatus

Packet communication device, packet communication system, packet communication system, packet communication module, data processor, and data transfer system

Micro controller for decompressing and compressing variable length codes via a compressed code dictionary

Data processing apparatus and shading apparatus

Memory access methods in a unified memory system

Packet communication apparatus

Packet communication apparatus

Data processor having unified memory architecture using register to optimize memory access

Memory access methods in a unified memory system

YOSHIMURA KENTARO

Vehicle control system

HITACHI ENG CO LTD

Graphics drawing device and method