Inventor

ADL-TABATABAI ALI-REZA

US116 patents

⚠️ This page may combine multiple inventors who share the name “ADL-TABATABAI ALI-REZA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADL-TABATABAI ALI-REZA

INTEL CORP

Method for performing dynamic optimization of computer code

Memory reclamation with optimistic concurrency

Method of run-time tracking of object references in Java programs

Method of run-time tracking of object references in Java programs

Object based conflict detection in a software transactional memory

Method for eliminating common subexpressions from java byte codes

Protecting shared variables in a software transactional memory system

Hardware acceleration for a software transactional memory system

Thread synchronization methods and apparatus for managed run-time environments

Method for fast exception handling

Mechanisms to accelerate transactions using buffered stores

Method and apparatus to improve execution of a stored program

Method and apparatus to improve execution of a stored program

Transactional memory with automatic object versioning

Multi-processor computing system that employs compressed cache lines&#39; worth of information and processor capable of use in said system

Software assisted nested hardware transactions

Mechanism to include hints within compressed data

Efficient non-transactional write barriers for strong atomicity

Hardware acceleration for a software transactional memory system

Method and apparatus for performing dynamic optimization for software transactional memory

Coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions

Thread synchronization with lock inflation methods and apparatus for managed run-time environments

Methods and apparatus for optimizing the operating speed and size of a computer program

Method for implementing dynamic type checking

Processor and memory controller capable of use in computing system that employs compressed cache lines&#39; worth of information

Performing mode switching in an unbounded transactional memory (UTM) system

Compressing data in a cache memory

Dynamic performance monitoring-based approach to memory management

Mechanism to store reordered data with compression

GRAY JAN

Hardware accelerated transactional memory system with open nested transactions

Performing mode switching in an unbounded transactional memory (UTM) system

Private memory regions and coherence optimizations

Efficient garbage collection and exception handling in a hardware accelerated transactional memory system

Wait loss synchronization

SAHA BRATIN

Increasing functionality of a reader-writer lock

Concurrent thread execution using user-level asynchronous signaling

Hardware acceleration of a write-buffering software transactional memory

Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM

Accelerating software lookups by using buffered or ephemeral stores

YAMADA KOICHI

Operating system virtual memory management for hardware transactional memory

Operating system virtual memory management for hardware transactional memory

WELC ADAM

Hybrid transactions for low-overhead speculative parallelization

Mechanism for irrevocable transactions

WANG CHENG

Mechanism for software transactional memory commit/abort in unmanaged runtime environment

Efficient and consistent software transactional memory

ADL-TABATABAI ALI-REZA

Mechanisms to accelerate transactions using buffered stores

Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata

NI YANG

Method and apparatus to facilitate shared pointers in a heterogeneous platform

SHPEISMAN TATIANA

Dynamic optimization for removal of strong atomicity barriers

RAJAGOPALAN MOHAN

Systems and methods for data-parallel processing

Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system

Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information