Inventor

LIEN CHUEN-DER

US155 patents

⚠️ This page may combine multiple inventors who share the name “LIEN CHUEN-DER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIEN CHUEN-DER

INTEGRATED DEVICE TECH

DRAM circuit with separate refresh memory

Electrostatic discharge protection circuit

Cam circuit with error correction

Ternary CAM array

Structure for controlling threshold voltage of MOSFET

Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same

Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same

Content addressable memory (CAM) devices that utilize multi-port CAM cells and control logic to support multiple overlapping search cycles that are asynchronously timed relative to each other

Quad CAM cell with minimum cell size

Cam array with minimum cell size

Five-transistor SRAM cell

Low-power content addressable memory cell

Methods for fabricating a bonding pad having improved adhesion to an underlying structure

Structure for fabricating a bonding pad having improved adhesion to an underlying structure

Method for fabricating air gap with borderless contact

Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow

Semiconductor device having programmable interconnect layers

ESD damage protection using a clamp circuit

Look-ahead built-in self tests with temperature elevation of functional elements

Look-ahead built-in self tests

Binary and ternary non-volatile CAM

Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors

Cam circuit with separate memory and logic operating voltages

Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same

Integrated output driver circuits having current sourcing and current sinking characteristics that inhibit power bounce and ground bounce

CAM circuit with radiation resistance

CAM circuit with separate memory and logic operating voltages

Increasing priority encoder speed using the most significant bit of a priority address

Pipelining a content addressable memory cell array for low-power operation

CAM array with minimum cell size

Testing method and apparatus for identifying disturbed cells within a memory cell array

Compact static RAM cell

SRAM cell using thin gate oxide pulldown transistors

Method of making a 6-transistor compact static ram cell

Memory cell having asymmetrical source/drain pass transistors and method for operating same

Changed device model electrostatic discharge protection circuit for output drivers and method of implementing same

Method for making high speed poly-emitter bipolar transistor

Static random-access memory cell with capacitive coupling to reduce sensitivity to radiation

Bitline pull-up circuit operable in a low-resistance test mode

CMOS output driver

Clock generator and method for providing reliable clock signal using array of MEMS resonators

Electrical overstress (EOS) and electrostatic discharge (ESD) protection circuit and method of use

Method for forming CMOS device with self-aligned contacts and region formed using salicide process

Method for forming cmos device with self-aligned contacts and region formed using salicide process

Content addressable memory (CAM) devices that support power saving longest prefix match operations and methods of operating same

ESD protection circuit

High speed buffer circuit with improved noise immunity

Identical gate conductivity type static random access memory cell

INTEGRATED DEVICES TECHNOLOGY

DRAM-based CAM cell using 3T or 4T DRAM cells

INTEGRATED DEVICE TECHNOLOGY

Parallel manufacturing of semiconductor devices and the resulting structure