Inventor

CHOI JEONG YEOL

US17 patents

⚠️ This page may combine multiple inventors who share the name “CHOI JEONG YEOL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOI JEONG YEOL

INTEGRATED DEVICE TECH

Structure for controlling threshold voltage of MOSFET

Selective diffusion process for forming both n-type and p-type gates with a single masking step

Methods, apparatus and computer program products for modeling integrated circuit devices having reduced linewidths

SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same

Compact ternary content addressable memory cell

Method for fabricating a CMOS device

Structure for improving latch-up immunity and interwell isolation in a semiconductor device

Method for forming gate oxides of different thicknesses

Mosfet with raised source and drain regions

CMOS process forming wells after gate formation

CMOS structure having a gate without spacers

Method of improving the reliability of low-voltage programmable antifuse

Method for improving latch-up immunity and interwell isolation in a semiconductor device

Method for fabricating a CMOS device

High density MOSFET with raised source and drain regions

Method of forming an oxide layer

SEMES CO LTD

Substrate transport apparatus