Inventor

ARTIERI ALAIN

FR42 patents

⚠️ This page may combine multiple inventors who share the name “ARTIERI ALAIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ARTIERI ALAIN

SGS THOMSON MICROELECTRONICS

Picture processing system

Apparatus and method for decompressing high definition pictures

Multitask processor architecture having a plurality of instruction pointers

System for converting digital television signals with insertion of interactive menus

Dual-port memory

Dual-port memory

Device for converting a line scanning into a vertical saw tooth scanning through stripes

Transposition memory for a data processing circuit

Serializer/deserializer with a triangular matrix

MPEG decoder with reduced memory capacity

System for rearranging sequential data words from an initial order to an arrival order in a predetermined order

Image processing system including a variable size memory bus

System for writing words into memory in first order and concurrently reading words from memory in second order based on input output ranks of words

Pixel matrix filter

Circuit and a method for selecting the kappa greatest data in a data sequence

System for rearranging sequential data words from an initial order to an arrival order in a predetermined order

Signal processing integrated circuit for row and column addition of matrices of digital values

QUALCOMM INC

Dynamic memory scheduling routine with enhanced bank-group batching

Method and apparatus for virtualized control of a shared system cache

Power-reducing memory subsystem having a system cache and local resource management

System and method for a shared cache with adaptive partitioning

Method and apparatus for flexible cache partitioning by sets and ways into component caches

Method and apparatus for a shared cache with dynamic partitioning

Dram-aware caching

Optimized error-correcting code (ECC) for data protection

Dynamic link error protection in memory systems

Dynamic link error protection in memory systems

Memory bank group interleaving

Optimized error-correcting code (ECC) for data protection

Power management using duty cycles

Power-reducing memory subsystem having a system cache and local resource management

Multimedia compressed frame aware cache replacement policy

Rank interleaving for system meta mode operations in a dynamic random access memory (DRAM) memory device

ST MICROELECTRONICS INC

Programmed memory with improved speed and power consumption

Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation

Synchronization pulse generator with forced output

FRANCE ETAT

Process and circuit for block matching in two-dimensional picture signals

Method and circuit for filtering signals representative of a picture

ST MICROELECTRONICS SA

FIFO memory architecture and method for the management of the same

Method of executing concurrent tasks by a subsystem managed by a central processor

SGS THOMPSON MICROELECTRONICS

Clock frequency doubler

ARTIERI ALAIN

Composite electronic circuit assembly