Inventor

FILIPPI RONALD G

US93 patents

⚠️ This page may combine multiple inventors who share the name “FILIPPI RONALD G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FILIPPI RONALD G

IBM

Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer

Structure and method for monitoring stress-induced degradation of conductive interconnects

Process for producing metal interconnections and product produced thereby

Process of enclosing via for improved reliability in dual damascene interconnects

Electromigration resistant power distribution network

Subtractive etch interconnects

Interconnect structure having subtractive etch feature and damascene feature

Gas dielectric structure forming methods

Electrically porous on-chip decoupling/shielding layer

Process for fabricating a metallization structure

Multiple device test layout

Interconnect structure having subtractive etch feature and damascene feature

Interconnect structure having substractive etch feature and damascene feature

High performance refractory metal / copper interconnects to eliminate electromigration

Selective local metal cap layer formation for improved electromigration behavior

E-fuse with hybrid metallization

Graphene and metal interconnects with reduced contact resistance

Graphene and metal interconnects

E-fuse with hybrid metallization

E-fuse structures and methods of manufacture

Electronic fuse having a damaged region

Electronic fuse vias in interconnect structures

Method of forming electronic fuse line with modified cap

Structure and method of forming electrically blown metal fuses for integrated circuits

Extrusion failure monitor structures

Semiconductor wiring structures including dielectric cap within metal cap layer

Back-end electrically programmable fuse

TSV deep trench capacitor and anti-fuse structure

Interconnect structure with enhanced reliability

Selective local metal cap layer formation for improved electromigration behavior

Semiconductor article having a zig-zag guard ring and method of forming the same

Interconnect with hybrid metallization

Selective local metal cap layer formation for improved electromigration behavior

Modified via bottom for beol via efuse

Selective local metal cap layer formation for improved electromigration behavior

GLOBALFOUNDRIES INC

Interconnect structures with variable dopant levels

Alternate dual damascene method for forming interconnects

Structure with air gap crack stop

Mechanically anchored backside C4 pad

Metal fuse structure for improved programming capability

Graphene-metal E-fuse

FILIPPI RONALD G

Stacked via structure for metal fuse applications

Electromigration immune through-substrate vias

Anti-fuse structure and fabrication

BONILLA GRISELDA

Metal fuse structure for improved programming capability

Interconnect structure for integrated circuits having enhanced electromigration resistance

Method to resolve hollow metal defects in interconnects

BAO JUNJING

Electronic anti-fuse

CHANDA KAUSHIK

Stress locking layer for reliable metallization

INFINEON TECHNOLOGIES AG

Device interconnection