Inventor
LAKSHMINARAYANA SHASHANK
IN5 patents
Patents
5 patentsUS11574382B2Feb 7, 2023
Programmable re-order buffer for decompression
INTEL CORP2 citations69
US11113783B2Sep 7, 2021
Programmable re-order buffer for decompression
INTEL CORP3 citations69
US11593069B2Feb 28, 2023
Use of a single instruction set architecture (ISA) instruction for vector normalization
INTEL CORP0 citations59
US11157238B2Oct 26, 2021
Use of a single instruction set architecture (ISA) instruction for vector normalization
INTEL CORP0 citations59
US11934797B2Mar 19, 2024
Mechanism to perform single precision floating point extended math operations
INTEL CORP0 citations48