Inventor

GANS DEAN

US54 patents

⚠️ This page may combine multiple inventors who share the name “GANS DEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GANS DEAN

MICRON TECHNOLOGY INC

Method and apparatus for adjusting control signal timing in a memory device

Method and system for adaptively adjusting control signal timing in a memory device

Method and apparatus for adjusting control signal timing in a memory device

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

Method and apparatus for testing SRAM memory cells

Adjustable I/O timing from externally applied voltage

Device and method for protecting an integrated circuit during an ESD event

Method, apparatus and system for voltage screening of integrated circuits

Memory with combined synchronous burst and bus efficient functionality

Methods and apparatuses for signal translation in a buffered memory

Frequency synthesis for memory input-output operations

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance

Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

Methods and apparatuses for signal translation in a buffered memory

Memory with combined synchronous burst and bus efficient functionality

Integrated circuit having forced substrate test mode with improved substrate isolation

Method and apparatus for synchronizing data from memory arrays

Method and apparatus for synchronizing data from memory arrays

Memory with combined synchronous burst and bus efficient functionality

Adjustable write voltage circuit for SRAMS

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory

Device and method for protecting an integrated circuit during an ESD event

Methods and apparatuses for signal translation in a buffered memory

Adjustable column address scramble using fuses

Frequency synthesis for memory input-output operations

Apparatuses and methods for asymmetric input/output interface for a memory

Apparatuses and methods for asymmetric input/output interface for a memory

Integrated circuit having forced substrate test mode with improved substrate isolation

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods including memory commands for semiconductor memories

Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory

Method and apparatus for synchronizing data from memory arrays

Adjustable column address scramble using fuses

Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory

LODESTAR LICENSING GROUP LLC

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

LOVETT SIMON J

Method and apparatus for synchronizing data from memory arrays

SUNRISE MEMORY CORP

Memory interface with configurable high-speed serial data lanes for high bandwidth memory