Inventor

AKAOGI TAKAO

JP95 patents

⚠️ This page may combine multiple inventors who share the name “AKAOGI TAKAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AKAOGI TAKAO

FUJITSU LTD

Semiconductor memory device for selecting and deselecting blocks of word lines

Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics

Clock control circuit for generating an internal clock signal with one or more external clock cycles being blocked out and a synchronous flash memory device using the same

Flash memory with improved erasability and its circuitry

Nonvolatile semiconductor memory

XOR CMOS logic gate

Nonvolatile semiconductor memory

Nonvolatile semiconductor memory

High speed decoder for flash memory

Decoder circuit

Burst mode flash memory

Substrate voltage control circuit for a flash memory

Non-volatile semiconductor memory device having floating gate

Nonvolatile semiconductor memory

Electrically erasable non-volatile semiconductor memory device for selective use in boot block type or normal type flash memory devices

Semiconductor memory device having redundant memory cells

Semiconductor memory device

Programmable semiconductor memory apparatus

Flash-erasable semiconductor memory device having improved reliability

Flash memory with improved erasability and its circuitry

Semiconductor memory device for selecting and deselecting blocks of word lines

Flash memory with improved erasability and its circuitry

Frasable non-volatile semiconductor memory device having read/write test function

Nonvolatile semiconductor memory for positively holding stored data

Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics

Flash-erasable semiconductor memory device having an improved reliability

Flash-erasable semiconductor memory device having an improved reliability

Negative voltage circuit for a flash memory

Decoder circuit of erasable programmable read only memory for avoiding erroneous operation caused by parasitic capacitors

ADVANCED MICRO DEVICES INC

Bank architecture for a non-volatile memory enabling simultaneous reading and writing

Multiple bank simultaneous operation for a flash memory

Wordline driver for flash memory read mode

Power-saving modes for memories

Low voltage read cascode for 2V/3V and different bank combinations without metal options for a simultaneous operation flash memory device

Reference cell bitline path architecture for a simultaneous operation flash memory device

Address transition detect timing architecture for a simultaneous operation flash memory device

Reference cell four-way switch for a simultaneous operation flash memory device

Wordline driver for flash electrically erasable programmable read-only memory (EEPROM)

Address transistion detect timing architecture for a simultaneous operation flash memory device

Array VT mode implementation for a simultaneous operation flash memory device

Power-saving modes for memories

Sense amplifier architecture for sliding banks for a simultaneous operation flash memory device

Word line decoding architecture in a flash memory

Burst read incorporating output based redundancy

SPANSION LLC

Method for minimizing false detection of states in flash memory devices

Memory device and method thereof

Flash memory programming using an indication bit to interpret state

NANTERO INC

Sense amplifiers

AKAOGI TAKAO

Local word line driver and flash memory array device thereof

LIN YA-FEN

Partial local self boosting for NAND