Inventor
RABIDOUX PAUL A
US38 patents
⚠️ This page may combine multiple inventors who share the name “RABIDOUX PAUL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
37 patentsUS6440801B1Aug 27, 2002
Structure for folded architecture pillar memory cell
IBM199 citations99
US6114725ASep 5, 2000
Structure for folded architecture pillar memory cell
IBM160 citations99
US6096598AAug 1, 2000
Method for forming pillar memory cells and device formed thereby
IBM200 citations99
US5945707AAug 31, 1999
DRAM cell with grooved transfer device
IBM127 citations99
US6387783B1May 14, 2002
Methods of T-gate fabrication using a hybrid resist
IBM134 citations98
US6221562B1Apr 24, 2001
Resist image reversal by means of spun-on-glass
IBM113 citations98
US6531724B1Mar 11, 2003
Borderless gate structures
IBM37 citations96
US6338934B1Jan 15, 2002
Hybrid resist based on photo acid/photo base blending
IBM126 citations96
US6114082ASep 5, 2000
Frequency doubling hybrid photoresist having negative and positive tone components and method of preparing the same
IBM81 citations96
US6110653AAug 29, 2000
Acid sensitive ARC and method of use
IBM72 citations96
US6037194AMar 14, 2000
Method for making a DRAM cell with grooved transfer device
IBM82 citations96
US6007968ADec 28, 1999
Method for forming features using frequency doubling hybrid resist and device formed thereby
IBM47 citations96
US6372412B1Apr 16, 2002
Method of producing an integrated circuit chip using frequency doubling hybrid photoresist and apparatus formed thereby
IBM16 citations93
US6319651B1Nov 20, 2001
Acid sensitive ARC and method of use
IBM36 citations93
US6313492B1Nov 6, 2001
Integrated circuit chip produced by using frequency doubling hybrid photoresist
IBM22 citations93
US6303272B1Oct 16, 2001
Process for self-alignment of sub-critical contacts to wiring
IBM50 citations93
US6245488B1Jun 12, 2001
Method for forming features using frequency doubling hybrid resist and device formed thereby
IBM15 citations93
US6210866B1Apr 3, 2001
Method for forming features using self-trimming by selective etch and device formed thereby
IBM22 citations93
US6207514B1Mar 27, 2001
Method for forming borderless gate structures and apparatus formed thereby
IBM46 citations93
US6200726B1Mar 13, 2001
Optimization of space width for hybrid photoresist
IBM33 citations93
US6194268B1Feb 27, 2001
Printing sublithographic images using a shadow mandrel and off-axis exposure
IBM41 citations93
US6184041B1Feb 6, 2001
Fused hybrid resist shapes as a means of modulating hybrid resist space width
IBM36 citations93
US6150256ANov 21, 2000
Method for forming self-aligned features
IBM49 citations93
US6100172AAug 8, 2000
Method for forming a horizontal surface spacer and devices formed thereby
IBM24 citations93
US5956597ASep 21, 1999
Method for producing SOI & non-SOI circuits on a single wafer
IBM28 citations93
US7176089B2Feb 13, 2007
Vertical dual gate field effect transistor
IBM36 citations92
US6798017B2Sep 28, 2004
Vertical dual gate field effect transistor
IBM20 citations92
US6627361B2Sep 30, 2003
Assist features for contact hole mask patterns
IBM29 citations92
US6440635B1Aug 27, 2002
Low “K” factor hybrid photoresist
IBM16 citations92
US6284439B1Sep 4, 2001
Method of producing an integrated circuit chip using low “k” factor hybrid photoresist and apparatus formed thereby
IBM24 citations92
US6190829B1Feb 20, 2001
Low “K” factor hybrid photoresist
IBM24 citations91
US6221704B1Apr 24, 2001
Process for fabricating short channel field effect transistor with a highly conductive gate
IBM19 citations84
US6759315B1Jul 6, 2004
Method for selective trimming of gate structures and apparatus formed thereby
IBM8 citations74
US6277543B1Aug 21, 2001
Method for forming features using frequency doubling hybrid resist and device formed thereby
IBM8 citations74
US6017810AJan 25, 2000
Process for fabricating field effect transistor with a self-aligned gate to device isolation
IBM10 citations74
US6426175B2Jul 30, 2002
Fabrication of a high density long channel DRAM gate with or without a grooved gate
IBM12 citations71
US6815737B2Nov 9, 2004
Method for selective trimming of gate structures and apparatus formed thereby
IBM0 citations52