Inventor
GEVA OFER
US12 patents
⚠️ This page may combine multiple inventors who share the name “GEVA OFER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS10831958B2Nov 10, 2020
Integrated circuit design with optimized timing constraint configuration
IBM3 citations68
US10657211B2May 19, 2020
Circuit generation based on zero wire load assertions
IBM1 citations57
US10572613B2Feb 25, 2020
Estimating timing convergence using assertion comparisons
IBM1 citations57
US11797740B2Oct 24, 2023
Even apportionment based on positive timing slack threshold
IBM0 citations56
US11775730B2Oct 3, 2023
Hierarchical large block synthesis (HLBS) filling
IBM0 citations54
US11296093B2Apr 5, 2022
Deep trench capacitor distribution
IBM0 citations54
US10325045B2Jun 18, 2019
Estimating timing convergence using assertion comparisons
IBM0 citations47
US12367331B2Jul 22, 2025
Approach to child block pinning
IBM0 citations41
US11030367B2Jun 8, 2021
Out-of-context feedback hierarchical large block synthesis (HLBS) optimization
IBM0 citations41
US10568203B2Feb 18, 2020
Modifying a circuit design
IBM0 citations33
US10546092B2Jan 28, 2020
Modifying a circuit design based on pre-routed top level design
IBM0 citations31