Inventor

HEYNE PATRICK

DE39 patents

⚠️ This page may combine multiple inventors who share the name “HEYNE PATRICK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HEYNE PATRICK

INFINEON TECHNOLOGIES AG

Delay locked loop for generating complementary clock signals

Circuit configuration for enabling a clock signal in a manner dependent on an enable signal

Synchronous integrated memory

Read latency control circuit

Delay locked loop

Integrable, controllable delay device, delay device in a control loop, and method for delaying a clock signal using a delay device

Semiconductor memory having a delay locked loop

Integrated memory having a row access controller for activating and deactivating row lines

Memory component with short access time

Circuit configuration for generating an output clock signal with optimized signal generation time

Integrated circuit for generating a phase-shifted output clock signal from a clock signal

Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits

Integrated circuit for producing two output clock signals at levels which do not overlap in time

Dynamic memory having two modes of operation

Circuit configuration and method for automatic recognition and elimination of word line/bit line short circuits

Delay locked loop

Method and circuit arrangement for resetting an integrated circuit

Method and logic/memory module for correcting the duty cycle of at least one control/reference signal

Current mirror circuit

Circuit configuration for compensating runtime and pulse-duty-factor differences between two input signals

Delay locked loop and method for setting a delay chain

Configuration for testing a plurality of memory chips on a wafer

Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process

Circuit configuration for programming a delay in a signal path

Synchronous integrated memory

Circuit configuration for generating a controllable output voltage

Voltage pump with switch-on control

Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device

SIEMENS AG

Integrated circuit with a phase locked loop

Integrated circuit with adjustable delay unit

Delivering a fine delay stage for a delay locked loop

Integrated circuit having adjustable delay units for clock signals

Optimized-delay multiplexer

Circuit configuration for producing complementary signals

Databus

QIMONDA AG

Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal

Delay circuit

INFINEON TECHNOLOGIES

Voltage generator with superimposed reference voltage and deactivation signals

INFINEON TECNOLOGIES AG

Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memory