Inventor

TSERN ELY

US93 patents

⚠️ This page may combine multiple inventors who share the name “TSERN ELY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSERN ELY

RAMBUS INC

Memory system topologies including a buffer device and an integrated circuit memory device

Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology

System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices

System featuring memory modules that include an integrated circuit buffer devices

System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices

Multiple channel modules and bus systems using same

Memory system including a point-to-point linked memory subsystem

Memory system topologies including a buffer device and an integrated circuit memory device

Memory with refresh logic to accommodate low-retention storage rows

Configurable width buffered module

Configurable width buffered module having a bypass circuit

Configurable width buffered module having flyby elements

System having a controller device, a buffer device and a plurality of memory devices

System featuring a master device, a buffer device and a plurality of integrated circuit memory devices

Multiple channel modules and bus systems using same

Data transmission using delayed timing signals

System including a buffered memory module

Memory system topologies including a buffer device and an integrated circuit memory device

Integrated circuit buffer device

Memory module having an integrated circuit buffer device

Buffer device and method of operation in a buffer device

Integrated circuit buffer device

Integrated circuit buffer device

Clock distribution network supporting low-power mode

Buffered memory having a control bus and dedicated data lines

Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device

Clock distribution network supporting low-power mode

Memory system topologies including a memory die stack

Memory system topologies including a buffer device and an integrated circuit memory device

Memory system topologies including a buffer device and an integrated circuit memory device

Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

High performance persistent memory

Memory system topologies including a buffer device and an integrated circuit memory device

Memory repair method and apparatus based on error code tracking

DRAM retention test method for dynamic error correction

Memory repair method and apparatus based on error code tracking

DRAM retention monitoring method for dynamic error correction

Memory system topologies including a buffer device and an integrated circuit memory device

System having a controller device, a buffer device and a plurality of memory devices

Method and apparatus for test and characterization of semiconductor components

Configurable width buffered module having switch elements

Memory system with threaded transaction support

High-performance, high-capacity memory systems and modules

TSERN ELY

User interface of a small touch sensitive display for an electronic data and communication device

Methods and circuits for dynamically scaling DRAM power and performance

Portable universal personal storage, entertainment, and communication device

SHAEFFER IAN

Memory system topologies including a buffer device and an integrated circuit memory device

Memory system topologies including a buffer device and an integrated circuit memory device

WARE FREDERICK A

Frequency-agile strobe window generation

BRYTE INC

Adaptive sleep system using data analytics and learning techniques to improve individual sleep conditions