Inventor

CHIDAMBARAM PR

US26 patents

⚠️ This page may combine multiple inventors who share the name “CHIDAMBARAM PR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIDAMBARAM PR

TEXAS INSTRUMENTS INC

Forming a retrograde well in a transistor to enhance performance of the transistor

Increased drive current by isotropic recess etch

Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel

Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel

Methods, systems and structures for forming improved transistors

Transistor fabrication methods using reduced width sidewall spacers

Drain extended MOS transistors and methods for making the same

Transistor fabrication methods using dual sidewall spacers

Drive current improvement from recessed SiGe incorporation close to gate

System and method for improved dopant profiles in CMOS transistors

Forming a retrograde well in a transistor to enhance performance of the transistor

Nitrogen based implants for defect reduction in strained silicon

Method for producing low/high voltage threshold transistors in semiconductor processing

Method of providing polysilicon spacer for implantation

Versatile system for limiting electric field degradation of semiconductor structures

QUALCOMM INC

System and method of manufacturing a fin field-effect transistor having multiple fin heights

Local interconnect structures for high density

Bone frame, low resistance via coupled metal oxide-metal (MOM) orthogonal finger capacitor

Complementary back end of line (BEOL) capacitor

Transistor with a diffusion barrier

FinFET with backgate, without punchthrough, and with reduced fin height variation

Capacitor using middle of line (MOL) conductive layers

Capacitor using middle of line (MOL) conductive layers

System and method of varying gate lengths of multiple cores

System and method of varying gate lengths of multiple cores

PATEL PRAYAG B

Standard cell architecture using double poly patterning for multi VT devices