Inventor

LIU CHIA-CHU

TW41 patents

⚠️ This page may combine multiple inventors who share the name “LIU CHIA-CHU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU CHIA-CHU

TAIWAN SEMICONDUCTOR MFG CO LTD

Dummy gate structure and methods thereof

Dummy gate structure and methods thereof

Dummy gate structure and methods thereof

Method for removing semiconductor fins using alternating masks

Method for manufacturing semiconductor device and system for performing the same

Method for manufacturing semiconductor device and system for performing the same

Inline focus monitoring

Dual critical dimension patterning

Dummy gate structure and methods thereof

Feature patterning using pitch relaxation and directional end-pushing with ion bombardment

Feature patterning using pitch relaxation and directional end-pushing with ion bombardment

Method of fabricating field effect transistor having non-orthogonal gate electrode

Method of fabricating field effect transistor having non-orthogonal gate electrode

Methods for small trench patterning using chemical amplified photoresist compositions

Semiconductor device with biased feature

System and method of circuit layout for multiple cells

Method and structure for gap filling improvement

Method and structure for gap filling improvement

Method for removing semiconductor fins using alternating masks

Method of making a structure

Multi-gate transistor device including a plurality of gate lines with bridge portion and method for fabricating the same

TAIWAN SEMICONDUCTOR MFG

Method for improving resist pattern peeling

Methods for small trench patterning using chemical amplified photoresist compositions

Enhanced FinFET process overlay mark

Method of defining an intensity selective exposure photomask

Method for etching an ultra thin film

Integrated circuit method with triple patterning

Method for making a lithography mask

Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication

LIU CHIA-CHU

System and method of circuit layout for multiple cells

Semiconductor device with biased feature

Method of forming a FinFET device

Field effect transistors and method of forming the same

Electrical-free dummy gate

Integrated circuit method with triple patterning

Semiconductors structure with elements having different widths and methods of making the same

WANG CHUNG-MING

Method of lithography process with an under isolation material layer

Method of forming a resist pattern with multiple post exposure baking steps

HSIEH CHI-WEN

Enhanced FinFET process overlay mark

CHANG YA HUI

Methods for small trench patterning using chemical amplified photoresist compositions

LIU YU-LUN

Method and apparatus for developing process