Inventor

CHEN KUEI-SHUN

TW111 patents

⚠️ This page may combine multiple inventors who share the name “CHEN KUEI-SHUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN KUEI-SHUN

TAIWAN SEMICONDUCTOR MFG CO LTD

Method for improving circuit layout for manufacturability

Method of fabricating semiconductor device with reduced trench distortions

Method and structure for mandrel and spacer patterning

Pattern fidelity enhancement

Pattern fidelity enhancement with directional patterning technology

Directional patterning methods

Dummy gate structure and methods thereof

Dummy gate structure and methods thereof

Dummy gate structure and methods thereof

Method for integrated circuit patterning

Overlay measurement and compensation in semiconductor fabrication

Method for removing semiconductor fins using alternating masks

Pattern fidelity enhancement

Method of fabricating semiconductor device with reduced trench distortions

Method of patterning a film layer

Method and structure for mandrel and spacer patterning

Method of fabricating reticle

Method of fabricating reticle

Exposure method of wafer substrate, manufacturing method of semiconductor device, and exposure tool

Method for integrated circuit patterning

Lithography process and system with enhanced overlay quality

Method of fabricating semiconductor device

Method of fabricating semiconductor device with reduced trench distortions

Pattern fidelity enhancement

Method of fabricating reticle

Method of fabricating semiconductor device with reduced trench distortions

Method of fabricating semiconductor device with reduced trench distortions

Pattern fidelity enhancement with directional patterning technology

Dummy gate structure and methods thereof

TAIWAN SEMICONDUCTOR MFG

Method utilizing compensation features in semiconductor processing

Method for improving resist pattern peeling

Dummy vias for damascene process

Method of improving via filling uniformity in isolated and dense via-pattern regions

Dummy vias for damascene process

Intensity selective exposure method and apparatus

Utilization of electric field with isotropic development in photolithography

Method of pattern formation in semiconductor fabrication

Method of heating semiconductor wafer to improve wafer flatness

Semiconductor device with scattering bars adjacent conductive lines

Enhanced FinFET process overlay mark

Method of defining an intensity selective exposure photomask

LIU CHIA-CHU

System and method of circuit layout for multiple cells

Semiconductor device with biased feature

Method of forming a FinFET device

Field effect transistors and method of forming the same

LIU GEORGE

Intensity selective exposure photomask

Semiconductor structure and method and tool for forming the semiconductor structure

Intensity selective exposure photomask

HSIEH CHI-WEN

Enhanced FinFET process overlay mark

LUNG YUAN-HSIANG

Metal cut process flow