Inventor
LEE RINUS TEK PO
US12 patents
⚠️ This page may combine multiple inventors who share the name “LEE RINUS TEK PO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
6 patentsUS10134739B1Nov 20, 2018
Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array
GLOBALFOUNDRIES INC21 citations93
US10211045B1Feb 19, 2019
Microwave annealing of flowable oxides with trap layers
GLOBALFOUNDRIES INC5 citations71
US10896853B2Jan 19, 2021
Mask-free methods of forming structures in a semiconductor device
GLOBALFOUNDRIES INC0 citations62
US10418365B2Sep 17, 2019
Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array
GLOBALFOUNDRIES INC1 citations62
US10204904B2Feb 12, 2019
Methods, apparatus and system for vertical finFET device with reduced parasitic capacitance
GLOBALFOUNDRIES INC1 citations62
US10134876B2Nov 20, 2018
FinFETs with strained channels and reduced on state resistance
GLOBALFOUNDRIES INC1 citations49
GLOBALFOUNDRIES US INC
4 patentsUS11362178B2Jun 14, 2022
Asymmetric source drain structures
GLOBALFOUNDRIES US INC0 citations62
US11145716B1Oct 12, 2021
Semiconductor devices with low resistance gate structures
GLOBALFOUNDRIES US INC0 citations62
US11004953B2May 11, 2021
Mask-free methods of forming structures in a semiconductor device
GLOBALFOUNDRIES US INC0 citations62
US11094598B2Aug 17, 2021
Multiple threshold voltage devices
GLOBALFOUNDRIES US INC0 citations58