P

Inventor

CHABINYC MICHAEL L

US36 patents
⚠️ This page may combine multiple inventors who share the name “CHABINYC MICHAEL L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PALO ALTO RES CT INC

25 patents
US7087444B2Aug 8, 2006

Method for integration of microelectronic components with microfluidic devices

PALO ALTO RES CT INC70 citations97
US7566899B2Jul 28, 2009

Organic thin-film transistor backplane with multi-layer contact structures and data lines

PALO ALTO RES CT INC37 citations92
US7136216B1Nov 14, 2006

Dual-stage tape-sealing of microcells or channels for display applications

PALO ALTO RES CT INC30 citations92
US7019328B2Mar 28, 2006

Printed transistors

PALO ALTO RES CT INC16 citations92
US6921679B2Jul 26, 2005

Electronic device and methods for fabricating an electronic device

PALO ALTO RES CT INC18 citations92
US6872588B2Mar 29, 2005

Method of fabrication of electronic devices using microfluidic channels

PALO ALTO RES CT INC31 citations92
US7662708B2Feb 16, 2010

Self-assembled interconnection particles

PALO ALTO RES CT INC8 citations84
US7586080B2Sep 8, 2009

Producing layered structures with layers that transport charge carriers in which each of a set of channel regions or portions operates as an acceptable switch

PALO ALTO RES CT INC12 citations84
US7688876B2Mar 30, 2010

Self-forming microlenses for VCSEL arrays

PALO ALTO RES CT INC7 citations74
US7327774B2Feb 5, 2008

Self-forming microlenses for VCSEL arrays

PALO ALTO RES CT INC8 citations74
US7223700B2May 29, 2007

Method for fabricating fine features by jet-printing and surface treatment

PALO ALTO RES CT INC9 citations74
US7755156B2Jul 13, 2010

Producing layered structures with lamination

PALO ALTO RES CT INC3 citations63
US7525194B2Apr 28, 2009

System including self-assembled interconnections

PALO ALTO RES CT INC4 citations63
US7504331B2Mar 17, 2009

Method of fabricating self-assembled electrical interconnections

PALO ALTO RES CT INC5 citations63
US7358530B2Apr 15, 2008

Thin-film transistor array with ring geometry

PALO ALTO RES CT INC2 citations63
US7125495B2Oct 24, 2006

Large area electronic device with high and low resolution patterned film features

PALO ALTO RES CT INC6 citations63
US7361529B2Apr 22, 2008

Transistor production using semiconductor printing fluid

PALO ALTO RES CT INC4 citations62
US7129181B2Oct 31, 2006

Sub-resolution gaps generated by controlled over-etching

PALO ALTO RES CT INC4 citations58
US7838865B2Nov 23, 2010

Method for aligning elongated nanostructures

PALO ALTO RES CT INC1 citations52
US7838933B2Nov 23, 2010

Printing method for high performance electronic devices

PALO ALTO RES CT INC1 citations52
US7786430B2Aug 31, 2010

Producing layered structures with layers that transport charge carriers

PALO ALTO RES CT INC1 citations52
US7425734B2Sep 16, 2008

Thin-film transistor array with ring geometry

PALO ALTO RES CT INC0 citations52
US7405424B2Jul 29, 2008

Electronic device and methods for fabricating an electronic device

PALO ALTO RES CT INC0 citations52
US7980195B2Jul 19, 2011

Transistor production using semiconductor printing fluid

PALO ALTO RES CT INC0 citations51
US8000613B2Aug 16, 2011

Flexible nanowire sensors and field-effect devices for testing toner

PALO ALTO RES CT INC0 citations50

CHABINYC MICHAEL L

4 patents

UNIV CALIFORNIA

4 patents

XEROX CORP

1 patent

NG TSE NGA

1 patent

NG TSE N

1 patent