Inventor

KAPOOR ASHOK K

US87 patents

⚠️ This page may combine multiple inventors who share the name “KAPOOR ASHOK K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAPOOR ASHOK K

LSI LOGIC CORP

Hexagonal architecture

Architecture having diamond shaped or parallelogram shaped cells

CAD for hexagonal architecture

Hexagonal field programmable gate array architecture

Hexagonal DRAM array

Microelectronic integrated circuit including triangular CMOS &#34;nand&#34; gate device

Low dielectric constant insulation layer for integrated circuit structure and method of making same

Tri-directional interconnect architecture for SRAM

Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures

Automating photolithography in the fabrication of integrated circuits

Metal interconnect structures for use with integrated circuit devices to form integrated circuit structures

Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same

Hexagonal sense cell architecture

Method of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric deposition

Low dielectric constant insulation layer for integrated circuit structure and method of making same

Polydirectional non-orthoginal three layer interconnect architecture

Hexagonal architecture with triangular shaped cells

Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same

Low dielectric constant insulation layer for integrated circuit structure and method of making same

Process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps

Method for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereon

Triangular semiconductor or gate

Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product

MOSFET device with improved LDD region and method of making same

Product of process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps

Process and structure for reduction of channeling during implantation of source and drain regions in formation of MOS integrated circuit structures

Low dielectric constant insulation layer for integrated circuit structure and method of making same

Combined JFET and MOS transistor device, circuit

Process for forming low dielectric constant insulation layer on integrated circuit structure

Minimum metal consumption power distribution network on a bonded die

Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cells

Programmable triangular shaped device having variable gain

Electrostatic discharge (ESD) structure and buffer driver structure for providing ESD and latchup protection for integrated circuit structures in minimized I/O space

Multilevel metallization structure for integrated circuit I/O lines for increased current capacity and ESD protection

Triangular semiconductor NAND gate

Method of fabricating insulated-gate field-effect transistors having different gate capacitances

NAT SEMICONDUCTOR CORP

Angled implant to build MOS transistors in contact holes

Method of fabricating polycrystalline silicon resistors having desired temperature coefficients

Process for forming self-aligned silicide base contact for bipolar transistor

Method of making extended silicide and external contact

Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer

Buried Schottky clamped transistor

DSM SOLUTIONS INC

Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys

Method for applying a stress layer to a semiconductor device and device formed therefrom

JFET device with virtual source and drain link regions and method of fabrication

FAIRCHILD CAMERA INSTR CO

Structure for inhibiting dopant out-diffusion

Method and structure for inhibiting dopant out-diffusion

FAIRCHILD SEMICONDUCTOR

Extended silicide and external contact technology

(unassigned)

Method of forming polysilicon local interconnects

GOLD STANDARD SIMULATIONS LTD

Variation resistant MOSFETs with superior epitaxial properties

Microelectronic integrated circuit including triangular CMOS "nand" gate device