Inventor
RYCHLIK BOHUSLAV
US77 patents
⚠️ This page may combine multiple inventors who share the name “RYCHLIK BOHUSLAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
QUALCOMM INC
24 patentsUS7962731B2Jun 14, 2011
Backing store buffer for the register save engine of a stacked register file
QUALCOMM INC22 citations93
US9361228B2Jun 7, 2016
Cache line compaction of compressed data segments
QUALCOMM INC18 citations92
US9626295B2Apr 18, 2017
Systems and methods for scheduling tasks in a heterogeneous processor cluster architecture using cache demand monitoring
QUALCOMM INC10 citations84
US7844804B2Nov 30, 2010
Expansion of a stacked register file using shadow registers
QUALCOMM INC8 citations84
US9355038B2May 31, 2016
Cache bank spreading for compression algorithms
QUALCOMM INC6 citations83
US9176572B2Nov 3, 2015
System and method for controlling central processing unit power with guaranteed transient deadlines
QUALCOMM INC9 citations83
US9218289B2Dec 22, 2015
Multi-core compute cache coherency with a release consistency memory ordering model
QUALCOMM INC11 citations82
US10503643B1Dec 10, 2019
Cache coherence with functional address apertures
QUALCOMM INC2 citations73
US10255181B2Apr 9, 2019
Dynamic input/output coherency
QUALCOMM INC5 citations73
US9690710B2Jun 27, 2017
System and method for improving a victim cache mode in a portable computing device
QUALCOMM INC2 citations73
US9684787B2Jun 20, 2017
Method and system for inferring application states by performing behavioral analysis operations in a mobile device
QUALCOMM INC5 citations73
US10261910B2Apr 16, 2019
Cache line compaction of compressed data segments
QUALCOMM INC2 citations72
US9792215B2Oct 17, 2017
Command-driven translation pre-fetch for memory management units
QUALCOMM INC3 citations71
US9489305B2Nov 8, 2016
System and method for managing bandwidth and power consumption through data filtering
QUALCOMM INC3 citations71
US9104411B2Aug 11, 2015
System and method for controlling central processing unit power with guaranteed transient deadlines
QUALCOMM INC5 citations71
US9824015B2Nov 21, 2017
Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media
QUALCOMM INC4 citations70
US8600754B2Dec 3, 2013
System and method of providing voice updates from a navigation system that recognizes an active conversation
QUALCOMM INC4 citations63
US7647481B2Jan 12, 2010
Reducing power by shutting down portions of a stacked register file
QUALCOMM INC5 citations63
US7613906B2Nov 3, 2009
Advanced load value check enhancement
QUALCOMM INC4 citations63
US10338837B1Jul 2, 2019
Dynamic mapping of applications on NVRAM/DRAM hybrid memory
QUALCOMM INC1 citations62
US10747671B1Aug 18, 2020
System and method for intelligent tile-based prefetching of image frames in a system on a chip
QUALCOMM INC1 citations60
US9442774B2Sep 13, 2016
Thermally driven workload scheduling in a heterogeneous multi-processor system on a chip
QUALCOMM INC2 citations59
US11636057B2Apr 25, 2023
Data re-encoding for energy-efficient data transfer in a computing device
QUALCOMM INC1 citations58
US12182036B2Dec 31, 2024
Providing content-aware cache replacement and insertion policies in processor-based devices
QUALCOMM INC0 citations57
RAMBUS INC
7 patentsUS11204863B2Dec 21, 2021
Memory component that performs data write from pre-programmed register
RAMBUS INC21 citations94
US9658953B2May 23, 2017
Single command, multiple column-operation memory device
RAMBUS INC15 citations90
US10552310B2Feb 4, 2020
Single command, multiple column-operation memory device
RAMBUS INC6 citations84
US8838900B2Sep 16, 2014
Atomic-operation coalescing technique in multi-chip systems
RAMBUS INC2 citations63
US12189523B2Jan 7, 2025
Command-differentiated storage of internally and externally sourced data
RAMBUS INC0 citations62
US11748252B2Sep 5, 2023
Data write from pre-programmed register
RAMBUS INC0 citations62
US11720485B2Aug 8, 2023
DRAM with command-differentiated storage of internally and externally sourced data
RAMBUS INC0 citations62
RYCHLIK BOHUSLAV
7 patentsUS8555039B2Oct 8, 2013
System and method for using a local condition code register for accelerating conditional instruction execution in a pipeline processor
RYCHLIK BOHUSLAV35 citations94
US8595014B2Nov 26, 2013
Providing audible navigation system direction updates during predetermined time windows so as to minimize impact on conversations
RYCHLIK BOHUSLAV22 citations92
US8650426B2Feb 11, 2014
System and method for controlling central processing unit power in a virtualized system
RYCHLIK BOHUSLAV15 citations83
US8689037B2Apr 1, 2014
System and method for asynchronously and independently controlling core clocks in a multicore central processing unit
RYCHLIK BOHUSLAV7 citations82
US9563250B2Feb 7, 2017
System and method for controlling central processing unit power based on inferred workload parallelism
RYCHLIK BOHUSLAV4 citations71
US9092358B2Jul 28, 2015
Memory management unit with pre-filling capability
RYCHLIK BOHUSLAV4 citations68
US8665642B2Mar 4, 2014
Pattern-sensitive coding of data for storage in multi-level memory cells
RYCHLIK BOHUSLAV2 citations62
INTEL CORP
3 patentsUS7363467B2Apr 22, 2008
Dependence-chain processing using trace descriptors having dependency descriptors
INTEL CORP40 citations92
US7228402B2Jun 5, 2007
Predicate register file write by an instruction with a pending instruction having data dependency
INTEL CORP15 citations81
US6668306B2Dec 23, 2003
Non-vital loads
INTEL CORP5 citations60
ANDERSON JON JAMES
2 patentsSUR SUMIT
2 patentsUS8775830B2Jul 8, 2014
System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on temperature
SUR SUMIT10 citations81
US9442773B2Sep 13, 2016
Thermally driven workload scheduling in a heterogeneous multi-processor system on a chip
SUR SUMIT3 citations68
REGINI EDOARDO
1 patentDIEFFENDERFER JAMES NORRIS
1 patentANDERSON JON J
1 patentDUROIU CRISTIAN
1 patentLIN QI
1 patentShowing the top 50 of 77 patents by PatentIndex Score.