Inventor

MA YANTAO

US102 patents

⚠️ This page may combine multiple inventors who share the name “MA YANTAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MA YANTAO

MICRON TECHNOLOGY INC

Multi-phase duty-cycle corrected clock signal generator and memory having same

Resistive memory

Method and apparatus for reducing oscillation in synchronous circuits

Method and apparatus for output data synchronization with system clock

Delay-locked loop (DLL) system for determining forward clock path delay

Clock signal and supply voltage variation tracking

Apparatuses and methods for providing constant DQS-DQ delay in a memory device

Clock signal and supply voltage variation tracking

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path

Apparatus and methods for altering the timing of a clock signal

Apparatuses and methods for changing signal path delay of a signal path responsive to changes in power

Clock signal generators having a reduced power feedback clock path and methods for generating clocks

Resistive memory

Multi-phase signal generator and method

Multi-phase signal generator and method

Periodic signal synchronization apparatus, systems, and methods

Resistive memory

Periodic signal synchronization apparatus, systems, and methods

Circuits, systems, and methods for reducing simultaneous switching output noise, power noise, or combinations thereof

State machine sensing of memory cells

Clock jitter compensated clock circuits and methods for generating jitter compensated clock signals

Periodic signal delay apparatus, systems, and methods

Delay-locked loop (DLL) system for determining forward clock path delay

Method and apparatus for reducing oscillation in synchronous circuits

Apparatuses and methods for providing constant DQS-DQ delay in a memory device

Apparatuses and methods for adjusting timing of signals

Apparatuses and methods for providing a signal with a differential phase mixer

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

Apparatuses and methods for providing a signal with a differential phase mixer

Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up

Apparatuses and methods for duty cycle adjustment

Apparatus and method for instant-on quadra-phase signal generator

Apparatuses and methods for adjusting timing of signals

Two-stage phase mixer circuit

Apparatuses and methods for providing clock signals

Apparatuses, methods, and circuits including a delay circuit

Power supply induced signal jitter compensation

Apparatuses and methods for duty cycle adjustment

MA YANTAO

Apparatus and methods for altering the timing of a clock signal

Apparatuses, circuits, and methods for reducing metastability in data synchronization

Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path

Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method

Resistive memory

Power supply induced signal jitter compensation

NANYA TECHNOLOGY CORP

Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method

Delay lock loop and delay lock method

WILLEY AARON

Clock signal generators having a reduced power feedback clock path and methods for generating clocks

Clock signal generators having a reduced power feedback clock path and methods for generating clocks