Inventor

DEHAEMER ERIC J

US35 patents

⚠️ This page may combine multiple inventors who share the name “DEHAEMER ERIC J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DEHAEMER ERIC J

INTEL CORP

Mechanism for managing multiple out-of-order packet streams in a PCI host bridge

Systems, methods and devices for work placement on processor cores

Configuring power management functionality in a processor

Controlling telemetry data communication in a processor

Enabling functional dependency in a multi-function device

Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Processors having virtually clustered cores and cache slices

Systems, methods and devices for work placement on processor cores

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

Peripheral device having a programmable identification configuration register

Systems and methods for in-field core failover

Multicore processor with a control register storing an indicator that two or more cores are to operate at independent performance states

Systems and methods for in-field core failover

Configuring power management functionality in a processor

Configuring power management functionality in a processor

Integrated circuit having processor and switch capabilities

System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis

System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis

Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states

Processors having virtually clustered cores and cache slices

Register interface for computer processor

Configuring power management functionality in a processor

Configuring power management functionality in a processor

System and method for dynamic data prefetching

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors

Centralized error signaling and logging

Enforcing a power consumption duty cycle in a processor

BHANDARU MALINI K

Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator

Dynamically computing an electrical design point (EDP) for a multicore processor

Providing energy efficient turbo operation of a processor

Dynamically controlling interconnect frequency in a processor

Method and apparatus for per core performance states

VARMA ANKUSH

Mechanism to provide workload and configuration-aware deterministic performance for microprocessors