Inventor
RAPHY RAY
US7 patents
Patents
7 patentsUS7519927B1Apr 14, 2009
Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations
IBM22 citations85
US7356793B2Apr 8, 2008
Genie: a method for classification and graphical display of negative slack timing test failures
IBM9 citations82
US7120888B2Oct 10, 2006
Method, system and storage medium for determining circuit placement
IBM14 citations81
US7305644B2Dec 4, 2007
Negative slack recoverability factor—a net weight to enhance timing closure behavior
IBM5 citations61
US7290233B2Oct 30, 2007
Method for netlist path characteristics extraction
IBM3 citations61
US7487484B2Feb 3, 2009
Method, system and storage medium for determining circuit placement
IBM2 citations60
US7823108B2Oct 26, 2010
Chip having timing analysis of paths performed within the chip during the design process
IBM5 citations58