Inventor

FROHBERG KAI

DE90 patents

⚠️ This page may combine multiple inventors who share the name “FROHBERG KAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FROHBERG KAI

ADVANCED MICRO DEVICES INC

Method for reducing resist poisoning during patterning of silicon nitride layers in a semiconductor device

Technique for forming a passivation layer prior to depositing a barrier layer in a copper metallization layer

Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress

Technique for controlling mechanical stress in a channel region by spacer removal

Field effect transistor having a stressed contact etch stop layer with reduced conformality

Technique for forming contact insulation layers and silicide regions with different characteristics

Test structure for OPC-related shorts between lines in a semiconductor device

Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress

Method and semiconductor structure for monitoring the fabrication of interconnect structures and contacts in a semiconductor device

Method of forming a field effect transistor comprising a stressed channel region

Method of forming an electrically conductive line in an integrated circuit

Field effect transistor comprising a stressed channel region and method of forming the same

Hybrid contact structure with low aspect ratio contacts in a semiconductor device

Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics

Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device

Method for patterning contact etch stop layers by using a planarization process

Method of forming an etch indicator layer for reducing etch non-uniformities

Method of forming a field effect transistor having a stressed channel region

Method for forming a metallization layer stack to reduce the roughness of metal lines

Technique for creating different mechanical strain by forming a contact etch stop layer stack having differently modified intrinsic stress

Technique for creating different mechanical strain by a contact etch stop layer stack with an intermediate etch stop layer

Method for forming a tungsten interconnect structure with enhanced sidewall coverage of the barrier layer

GLOBALFOUNDRIES INC

Method for forming semiconductor fuses in a semiconductor device comprising metal gates

Fabricating vias of different size of a semiconductor device by splitting the via patterning process

Semiconductor device comprising a contact structure based on copper and tungsten

Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics

Contact optimization for enhancing stress transfer in closely spaced transistors

Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size

Transistor having a high-k metal gate stack and a compressively stressed channel

Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region

Method for preventing the formation of electrical shorts via contact ILD voids

Semiconductor device including a vertical decoupling capacitor

Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias

GRIEBENOW UWE

Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region

Semiconductor device comprising a buried waveguide for device internal optical communication

Method for increasing penetration depth of drain and source implantation species for a given gate height

Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

FROHBERG KAI

High-K gate electrode structure formed after transistor fabrication by using a spacer

Methods of forming conductive contacts with reduced dimensions

Selective shrinkage of contact elements in a semiconductor device

Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach

FEUSTEL FRANK

Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom

Metallization system of a semiconductor device comprising extra-tapered transition vias

HEINRICH JENS

Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantation

Hybrid contact structure with low aspect ratio contacts in a semiconductor device

HUISINGA TORSTEN

Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction

BEYER SVEN

Contacts and vias of a semiconductor device formed by a hard mask and double exposure

RUELKE HARTMUT

Technique for forming a dielectric interlayer above a structure including closely spaced lines

RICHTER RALF

Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors

LETZ TOBIAS

Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge