Inventor

GAITHER BLAINE D

US53 patents

⚠️ This page may combine multiple inventors who share the name “GAITHER BLAINE D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GAITHER BLAINE D

HEWLETT PACKARD DEVELOPMENT CO

Method and apparatus for passing messages using a fault tolerant storage system

Cache coherence protocol for a multiple bus multiprocessor system

Method and apparatus for providing continued operation of a multiprocessor computer system after detecting impairment of a processor cooling device

Analyzing effectiveness of a computer cache by estimating a hit rate based on applying a subset of real-time addresses to a model of the cache

Cache system with groups of lines and with coherency for both single lines and groups of lines

Computer cache system with deferred invalidation

Computer performance improvement by adjusting a count used for preemptive eviction of cache entries

Hierarchical cache coherence directory structure

Method of optimization of CPU and chipset performance by support of optional reads by CPU and chipset

Computer performance improvement by adjusting a time used for preemptive eviction of cache entries

Method and apparatus for gathering three dimensional data with a digital imaging system

Controlling error propagation due to fault in computing node of a distributed computing system

Determining whether a right to use memory modules in a reliability mode has been acquired

Cache system with groups of lines and with coherency for both single lines and groups of lines

Processor and processor method of operation

Fault tolerant storage system having an interconnection fabric that also carries network traffic

Mask usable for snoop requests

Limiting the number of dirty entries in a computer cache

Systems and methods for pushing data

Performing a memory write of a data unit without changing ownership of the data unit

Mechanisms to sample shared-dirty-line addresses

GAITHER BLAINE D

Cache and method for cache bypass functionality

Switch module based non-volatile memory in a server

Datacenter workload evaluation

Reflective memory bridge for external computing nodes

Multiple processing elements

External cache operation based on clean castout messages

Computer cache system with stratified replacement

Computer cache system with stratified replacement

Computer cache system with stratified replacement

Method and system for moving active virtual partitions between computers

Address masking between users

Transactional cache memory system

Bit ordering for communicating an address on a serial fabric

HEWLETT PACKARD CO

Computer cache memory with classes and dynamic selection of replacement algorithms

Method and apparatus for virtualizing file access operations and other I/O operations

Methods and apparatus for improving system performance with a shared cache memory

Method and apparatus for clearing obstructions from computer system cooling fans

Method and apparatus for translating virtual path file access operations to physical file path access

System and method for recovery from address errors

Coherency protocol for computer cache

Dynamic trace driven object code optimizer

HEWLETT PACKARD ENTPR DEV LP

Split mode addressing a persistent memory

Fault tolerance for persistent main memory

Reflective memory bridge for external computing nodes

Controlling error propagation due to fault in computing node of a distributed computing system

BURROUGHS CORP

Extended address generating apparatus and method

Address generating apparatus and method

HEWLETT PACKARD DEVELOPMENT CO LP

Cache and method for cache bypass functionality

Implementing coherency with reflective memory